2013
DOI: 10.1016/j.nima.2013.07.029
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Characterization of EASIROC as front-end for the readout of the SiPM at the focal plane of the Cherenkov telescope ASTRI

Abstract: The Extended Analogue Silicon Photo-multiplier Integrated Read Out Chip, EASIROC, is a chip proposed as front-end of the camera at the focal plane of the imaging Cherenkov ASTRI SST-2M telescope prototype. This paper presents the results of the measurements performed to characterize EASIROC in order to evaluate its compliance with the ASTRI SST-2M focal plane requirements.In particular, we investigated the trigger time walk and the jitter effects as a function of the pulse amplitude. The EASIROC output signal … Show more

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Cited by 12 publications
(6 citation statements)
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“…The earlier FEE proposed for ASTRI was based on the extended analogue silicon photo-multiplier integrated read out chip (EASIROC) [11,12], a commercial application-specific integrated circuit (ASIC) for SiPM read out. Its characterization, performed with detailed measurements [13,14], proved that EASIROC fulfills the ASTRI requirements for the trigger time walk (5.5 ns), jitter (below 0.3 ns), electronic noise levels and electronic cross talk between channels. Moreover, EASIROC is capable of providing auto-triggering as required by the very short duration of the air shower events.…”
Section: Introductionmentioning
confidence: 87%
See 1 more Smart Citation
“…The earlier FEE proposed for ASTRI was based on the extended analogue silicon photo-multiplier integrated read out chip (EASIROC) [11,12], a commercial application-specific integrated circuit (ASIC) for SiPM read out. Its characterization, performed with detailed measurements [13,14], proved that EASIROC fulfills the ASTRI requirements for the trigger time walk (5.5 ns), jitter (below 0.3 ns), electronic noise levels and electronic cross talk between channels. Moreover, EASIROC is capable of providing auto-triggering as required by the very short duration of the air shower events.…”
Section: Introductionmentioning
confidence: 87%
“…In this set of measurements, we compared the CITIROC energy resolution with that of EASIROC and investigated the response linearity. Moreover, we measured the trigger efficiency as a function of the input charge to complete the characterization published in [14].…”
Section: Citiroc Characterizationmentioning
confidence: 99%
“…It is designed with a 0.35µm SiGe technology from AustriaMicroSystems. It is an evolution of the EASIROC (the Extended Analogue Silicon photomultiplier Integrated Read Out Chip) [6][7][8][9][10] which was available since 2010 and used in a variety of nuclear physics and astrophysics and medical imaging applications. Fine-tuning of each pixel gain is obtained adjusting the voltage applied to the SiPM through an 8-bit Digital-to-Analog Converter (DAC) ranging from 0 to 4.5 V. For each channel, two parallel AC coupled voltage preamplifiers the High Gain (HG) and Low gain (LG) electronics chains ensure the read out of the charge from 160 fC to 320 pC (i.e.…”
Section: The Citiroc Chipmentioning
confidence: 99%
“…It is designed with a 0.35 µm SiGe technology from AustriaMicroSystems. It is an evolution of the EASIROC (the Extended Analogue Silicon photo-multiplier Integrated Read Out Chip) [4][5][6][7][8] which was available since 2010 and used in a variety of nuclear physics and astrophysics and medical imaging applications. It has been adopted as front-end for the focal plane detectors of the ASTRI-Horn Cherenkov telescope [9,10] and, in this context, it was modified implementing the peak detector reading mode to satisfy the instrument requirements.…”
Section: Jinst 15 C04007mentioning
confidence: 99%
“…In contrast to the previous research, the current hot CTA experiment [5][6][7][8] makes use of a square arrangement. The labor expenses and installation challenges will be significantly decreased by this layout.…”
Section: Introductionmentioning
confidence: 99%