Characterization of GaAs self-aligned refractory-gate metal-semiconductor field-effect transistor (MESFET) integrated circuits

Abstract

GaAs metal-semiconductor field-effect transistors (MESFETs) and other integrated-circuit elements were characterized by including extensive process test sites on wafers with digital logic and memory circuits. A self-aligned, refractory-gate enhancement/depletion (E/D) process was employed which included 47SiF+ channel and source/drain implants, capless arsenic overpressure furnace annealing, WSi0.11 gate metal with in situ sputter cleaning, Ni-Au-Ge ohmic contacts, Si3N4 or SiO2 insulation, and Ni-Au wiring. On-water threshold voltage standard deviations as low as 31 mV for 1-μm E-FETs and 49 mV for 1-μm D-FETs were measured using 51-mm standard semi-insulating liquid-encapsulated Czochralski GaAs substrates. Threshold voltage control from wafer to wafer was of order 100 mV. Schottky diode barrier height was about 0.73 eV with an ideality of 1.2, although small self-aligned Schottky gates often showed excess conduction believed to occur at the gate edges. FET square-law coefficient, subthreshold leakage, gate capacitance, backgating, contact resistance, and wiring and insulation characteristics were also measured and found satisfactory. Fully functional 1-μm gate E/D MESFET circuits including a 4×4 bit multiplier, a 4×4 crosspoint switch, a 448-bit static RAM, and an integrated photodiode amplifier were demonstrated.

Ion implantation in Gallium Arsenide MESFET technology

“…Typical intrinsic time delay for such kind of inverter can he lower than I 00 p5 for I i.m gate length devices and the speed-power product below the pJ range (5). By controlling the doping level of the channel it is possible to obtain enhancement or depletion mode transistors.…”

Development of refractory ohmic contact materials for gallium arsenide compound semiconductors

“…Then, the contact was annealed by a laser beam at temperatures just at the NiGe melting point. The contact had good thermal stability during subsequent annealing at 350 8C for 6 h. However, this fabrication process was not compatible with the conventional GaAs metal semiconductor ®eld-effect transistor (MESFET) process [94]. In addition, the thermal stability required for VLSI devices was at temperatures of about 400 8C for 2 h.…”

Process Damage and Contamination Effects for Shallow Si Implanted GaAs

“…EL2 level has been shown to be the major electron trap in GaAs by various experiments (1)(2)(3)(4)(5)(6). Earlier studies have shown that this level is closely related to the dislocation density and causes fluctuations in the MESFET threshold voltage across the wafer (7-9).…”

“…Sputtered refractory gate materials are commonly used in the fabrication of submicron self-aligned MESFETs (1)(2)(3). "However, the sputter deposition and the subsequent reactive ion etching (RIE) of the gate can result in both damage and contamination of the GaAs surface (4).…”

“…The electrical activation and Hall mobility were measured at this first stage after buffered HF decapping of the SiNx as a reference for comparison to values obtained after processing (RIE, WSi= + RIE, and SiNx capped reannealing). The WSix deposition process consisted of a gentle oxygen then argon sputter cleaning of the GaAs surface, followed by dc magnetron sputter deposition of alternating layers from W and Si targets in argon at 10 mtorr (3). The RIE was performed in a parallel plate reactor using a CF4 (184 sccm)/O2 (16 sccm) chemistry at a pressure of 25 mtorr with plasma-induced self-biases ranging from 50 to 250V.…”