Characterization of Heavy Ion Induced SET Features in 22-nm FD-SOI Testing Circuits

Abstract

With device scaling-down, circuits appear more susceptible to transient faults especially for the bulk silicon process. Thus, FD-SOI technology has been widely popular in serious radiation environment due to its high radiation-tolerance inherence created by an additional BOX layer. In this work, seven different inverter chains with two kinds of core voltages, four kinds of channel areas and a stack inverter chain are designed to investigate the SET in advanced 22 nm FD-SOI CMOS technology. A NAND chain is also designed and used for comparison with inverter chains. The sensitivities of diverse SET targets are characterized with different core voltages and heavy-ion tilts. Results showed that the inverter size and the driving current can dominate the occurrence and width distribution of transient pulses. Besides, heavy-ion strike angle, LET, and charge sharing can also affect the pulse width. Though a high LET can deposit adequate energy, the widest pulses are measured in low-LET 84 Kr ion irradiation, rather than in high-LET ions' irradiation, which are attributed to the pulse quenching effect and being investigated by Hspice simulation. The LET dependency and low voltage induced SET widening are all observed in irradiation tests and verified by circuit-level pulse injection. All of the SET sensitive targets are distinguished. The results are highly effective for the designers to suppress and correct the SET-oriented errors to achieve a radiation robust system. INDEX TERMS Fully-depleted silicon-on-insulator (FD-SOI), heavy ions, inverter, single event transient.

Investigation of Single-Event-Transient Effects Induced by Heavy-Ion in All-Silicon DG-TFET

“…It is the amplification of charge deposited in the device when a heavy-ion strikes. It is defined as the ratio of collected charge (Q C ) and the deposited charge (Q d ) associated with heavy-ion [28]- [30].…”