Characterization of P-hit and N-hit single-event transient using heavy ion microbeam

Abstract

P-hit and N-hit single-event transients are investigated using heavy ion microbeam. A novel layout placement was implemented in the test chip to distinguish SETs originating from P-hit and N-hit. Experimental results indicate both the P-hit and N-hit SETs show an exponentiallike distribution in all target circuits. The SET cross sections and the average pulse width for P-hit and N-hit are also investigated. The well process, the transistor size and the layout topology significantly impact on the cross sections. Only the transistor size impacts on the average pulse width at low LET.

Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain

“…The generation of soft errors caused by radiation-induced single-event transients (SET) is a significant reliability challenge in modern complementary metal-oxide-semiconductor (CMOS) logic, both in space applications and in terrestrial applications [1][2][3]. As process feature sizes continue to shrink, clock frequencies continue to increase, node capacitance and supply voltage decrease, the critical charge of transient pulses is reduced [3][4][5], and waveforms are more easily captured and soft errors are formed. It has been reported that SET are the main cause of soft errors in space applications [6,7], and charge sharing may even affect multiple nodes and cause single-event multiple transients (SEMT) [8][9][10].…”

“…In Reference [14], pulse quenching can also affect SET. At the 65 nm process node, a lot of research has been done on the characterization of SET [3,[15][16][17][18], but in more advanced processes, the results of experimental measurements on SET are still few.…”

“…The load resistance and line capacitance of the test system cause large pulse distortion, and the on-chip measurement is believed to be a better solution in most applications, and Narasimham et al [20] invented a self-triggering technique for measuring SET pulses in 130 nm and 90 nm chips in Reference [12]. In other processes, there are also examples [3,9,13,14] of successful use of this measurement method. On the basis of this method, Huang et al [8] proposed a structure that can simultaneously measure multiple transient pulses, using eight capture circuits to share a self-trigger structure design, which can measure the SEMT.…”