Characterization of Plasma-Induced Damage of Selectively Recessed GaN/InAlN/AlN/GaN Heterostructures Using SiCl₄and SF₆

Abstract

We have investigated an inductively coupled plasma etching recipe using SiCl4 and SF6 with a resulting selectivity >10 for GaN in respect to InAlN. The formation of an etch-resistant layer of AlF3 on InAlN required about 1 min and was noticed by a 4-times-higher initial etch rate on bare InAlN barrier high electron mobility transistors (HEMTs). Comparing devices with and without plasma-treatment below the gate showed no degradation in drain current and gate leakage current for plasma exposure durations shorter than 30 s, indicating no plasma-induced damage of the InAlN barrier. Devices etched longer than the required time for the formation of the etch-resistant barrier exhibited a slight decrease in drain current and an increase in gate leakage current which saturated for longer etching-time durations. Finally, we could prove the quality of the recipe by recessing the highly doped 6 nm GaN cap layer of a GaN/InAlN/AlN/GaN heterostructure down to the 2 nm thin InAlN/AlN barrier layer.

Self‐aligned normally‐off metal–oxide–semiconductor n++GaN/InAlN/GaN high electron mobility transistors

“…We note that in the pulsed mode (100‐ns long pulses on the gate with the drain dc biased), if compared with the dc mode, up to a 25% decrease in I DS has been observed for both oxide systems, indicating some presence of deep levels (not shown). We consider these levels to be due to our low etch rate ECR RIE system with long overetching time in the gate opening, which was several times longer than the 30 s optimal time established for an inductively coupled plasma RIE system reported elsewhere .…”

“…Moreover, the unpassivated n ++ GaN cap provides enough free electrons to screen the quantum well (QW) two‐dimensional electron gas (2‐DEG) from the surface parasitic charging effects . On the other hand, for the recessed gate, an extensive leakage current may appear because of the electron tunneling and/or prolonged overetching of the barrier .…”

Plasma-assisted surface treatment for low-temperature annealed ohmic contact on AlGaN/GaN heterostructure field-effect transistors

“…The formation of the N vacancy caused by plasma treatment brings merit for the ohmic contact formation, which agrees well with some literatures using the conventional Ti/Al/Ti/Au or Ti/Al/Ni/Au stacks. [16][17][18][19] However, the annealing temperatures in their works were still around 800 • C. For the conventional Ti/Al-based metal stack, Ti will react with AlGaN layer under high temperature annealing to generate N vacancy in the AlGaN. [20] N vacancy then create a highly-doped n-type region in the proximity of the interface and decrease the contact resistance between Al and AlGaN.…”

Surface‐Oxide‐Controlled InAlGaN/GaN High‐Electron‐Mobility Transistors Using Al2O3‐Based Insulated‐Gate Structures with H2O Vapor Pretreatment

“…As shown in Table 2, the remarkable decrease in the mobility at the gate region of the Schottky-HEMT is attributed to the effect of plasma damage during the dry etching of the SiN passivation films. [43] Alternatively, in the case of MIS-HEMT, mobility degradation can be suppressed by depositing Al 2 O 3 films on the InAlGaN surface that functions as an etching stopper for SiN [44,45] ; moreover, the InAlGaN surface was prevented from exposure to the SF 6 plasma, leading to the improvement in I dmax .…”