Characterization of systematic MOSFET current factor mismatch caused by metal CMP dummy structures

Tuinhout, H.P.; Vertregt, M.

doi:10.1109/66.964317

Cited by 34 publications

(2 citation statements)

References 11 publications

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“…The coverage of transistors with metal layers can lead to mobility reduction due to incomplete annealing of interface states [257] and to variations in the stress pattern. tiling patterns) can cause stress [259]. Even wiring on top level (e.g.…”

Section: Offset Caused By Stressmentioning

confidence: 99%

Analog-to-Digital Conversion

Pelgrom

2010

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Section: Offset Caused By Stressmentioning

confidence: 99%

Analog-to-Digital Conversion

Pelgrom

2010

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“…INTRODUCTION Stress developed during integrated circuit fabrication and packaging can cause significant parameter shifts in sensitive analog and mixed signal ICs [1][2][3][4][5], and MOS transistors on (100) silicon are known to make excellent stress sensors that can monitor stress variation and chip and package "health" over time or provide sensor arrays that can provide high-resolution mapping of stress across the surface of specially designed test die [6-9]. Optimized piezoresistive FET (PiFET) rosettes on (100) silicon make use of the two largest piezoresistive coefficients (pi-coefficients), !…”

mentioning

confidence: 99%

Current dependence of the piezoresistive coefficients of CMOS FETs on (100) silicon

Hussain

Jaeger

Suhling

2014

2014 44th European Solid State Device Research Conference (ESSDERC)

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Orthogonal pairs of MOS transistor are well known to make excellent high-resolution stress sensors on (100) silicon. In order to properly design these sensors, circuit designers need an understanding of the operating point dependence of the piezoresistive coefficients (pi-coefficients) of the PMOS and NMOS devices. This paper presents the new results for the drain current dependence of the key pi-coefficients needed for application of CMOS stress sensors, namely ! 44 p and ! D n . It is demonstrated that uniaxial stress can be utilized to calibrate both the normal stress and shear stress sensors if the temperature is maintained sufficiently constant during calibration. Coefficient values are related to drain current, thereby providing the information necessary to make appropriate operating point choices for the design of CMOS stress sensors, and are also correlated with surface mobility in the devices.Keywords -CMOS; FET; piezoresistance; PiFET; stress sensor I. INTRODUCTION Stress developed during integrated circuit fabrication and packaging can cause significant parameter shifts in sensitive analog and mixed signal ICs [1][2][3][4][5], and MOS transistors on (100) silicon are known to make excellent stress sensors that can monitor stress variation and chip and package "health" over time or provide sensor arrays that can provide high-resolution mapping of stress across the surface of specially designed test die [6-9]. Optimized piezoresistive FET (PiFET) rosettes on (100) silicon make use of the two largest piezoresistive coefficients (pi-coefficients), ! 44 p of PMOS devices and ! D n = ! 11 n " ! 12 n of NMOS devices, to measure the in-plane normal stress difference and the in-plane shear stress on the surface of the silicon wafer, thereby providing highly localized stress measurements with high sensitivity. However, the MOS pi-coefficients of the sensor rosettes have typically been evaluated at only one operating point without any real data to guide the choice of operating conditions. This paper presents new results for the operating point dependence of these two important coefficients as well as ! S p = ! 11 p + ! 12 p of PMOS devices. Uniaxial stress is utilized to calibrate both the normal stress difference and shear stress sensors, and the piezoresistive coefficient values are characterized as a function of drain current thereby providing the information necessary to make appropriate operating point choices for the design of CMOS stress sensors. From a more fundamental point of view, it is shown that the magnitude of the ! 44 p exhibits a direct correlation with the PMOS channel mobility, whereas ! D n exhibits a nonlinear relation to NMOS channel mobility.II. BACKGROUND Conceptual layouts of the optimized PMOS and NMOS stress sensor rosettes [6,9] appear in Fig. 1 where the (0-90 o ) PMOS transistor pair measures the difference in the in-plane normal stresses , and the (±45 o ) NMOS pair measures in-plane shear stress . The stresses are resolved along the axes defined for the (001) silicon wafer in Fig. ...

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CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications

Müller¹,

Leblebici

2007

Analog Circuits and Signal Processing

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Characterization of systematic MOSFET current factor mismatch caused by metal CMP dummy structures

Cited by 34 publications

References 11 publications

Analog-to-Digital Conversion

Analog-to-Digital Conversion

Current dependence of the piezoresistive coefficients of CMOS FETs on (100) silicon

CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications

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