Characterization of the three-dimensional residual stress distribution in SiC bulk crystals by neutron diffraction

Xie, Xuejian; Chen, Xiufang; Liu, Fafu; Yang, Xiu; Xu, Xiangang; Wang, Hong; Li, Jian; Yu, Peng; Wang, Ruiqi

doi:10.1039/c7ce01552f

Cited by 19 publications

(10 citation statements)

References 21 publications

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“…The conclusion was reached that faster cooling rates lead to decreased BPD densities. Residual compressive stress in the <112¯0> direction in the range of −763 to −490 MPa and tensile stress in the <11¯00> direction between 673 to 2953 MPa was reported by Xie et al [10], indicating that a longer cooldown time after growth has an impact on BPD density due to annealing effects.…”

Section: Introductionmentioning

confidence: 92%

Analysis of the Basal Plane Dislocation Density and Thermomechanical Stress during 100 mm PVT Growth of 4H-SiC

et al. 2019

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Basal plane dislocations (BPDs) in 4H silicon carbide (SiC) crystals grown using the physical vapor transport (PVT) method are diminishing the performance of SiC-based power electronic devices such as pn-junction diodes or MOSFETs. Therefore, understanding the generation and movement of BPDs is crucial to grow SiC suitable for device manufacturing. In this paper, the impact of the cooldown step in PVT-growth on the defect distribution is investigated utilizing two similar SiC seeds and identical growth parameters except for a cooldown duration of 40 h and 70 h, respectively. The two resulting crystals were cut into wafers, which were characterized by birefringence imaging and KOH etching. The initial defect distribution of the seed wafer was characterized by synchrotron white beam X-ray topography (SWXRT) mapping. It was found that the BPD density increases with a prolonged cooldown time. Furthermore, small angle grain boundaries based on threading edge dislocation (TED) arrays, which are normally only inherited by the seed, were also generated in the case of the crystal cooled down in 70 h. The role of temperature gradients inside the crystal during growth and post-growth concerning the generation of shear stress is discussed and supported by numerical calculations.

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Section: Introductionmentioning

confidence: 92%

Analysis of the Basal Plane Dislocation Density and Thermomechanical Stress during 100 mm PVT Growth of 4H-SiC

et al. 2019

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Section: Resultsmentioning

confidence: 99%

“…The stress along <1−100> has a higher possible contribution to the crystal cracking. 16 And the lower temperature gradient decreases the thermal stress in the grown SiC ingot, which can be calculated according to the following equation: 15 where σ rr is the normal stress in the radial direction, σ φφ is the normal stress in the axial direction, σ zz is the normal stress in the azimuthal direction, σ rz is the shear stress, ε i,j is the strain rate, β is the thermal expansion coefficient, and T − T ref is the temperature difference. The decreased radial temperature gradient leads to a lower shear stress and a reduced possibility of cracks in the grown SiC ingot.…”

Section: Resultsmentioning

confidence: 99%

Control of the temperature field by double induction coils for growth of large-sized SiC single crystals via the physical vapor transport technique

et al. 2022

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“…The three substrates (Si, SiC, and diamond) and GaN were evaporated with AuSn/Ti on the surface. Si wafer was purchased from Sumco Corporation, while high quality diamond and 4H-SiC substrates were homegrown in Shandong University [27,28]. The p-type Si(111) and the 4H-SiC(0001) had resistivities of 10 and 10 8 Ω•cm −1 , respectively.…”

Section: Materials Growthmentioning

confidence: 99%

Reduced thermal boundary conductance in GaN-based electronic devices introduced by metal bonding layer

et al. 2021

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Achieving high interface thermal conductance is one of the biggest challenges in the nanoscale heat transport of GaN-based devices such as light emitting diodes (LEDs), and high electron mobility transistors (HEMTs). In this work, we experimentally measured thermal boundary conductance (TBC) at interfaces between GaN and the substrates with AuSn alloy as a commonly-used adhesive layer by time-domain thermoreflectance (TDTR). We find that the TBCs of GaN/Ti/AuSn/Ti/Si, GaN/ Ti/AuSn/Ti/SiC, and GaN/Ti/AuSn/Ti/diamond, are 16.5, 14.8, and 13.2 MW•m -2 •K -1 at room temperature, respectively. Our measured results show that the TBC of GaN/Ti/AuSn/Ti/SiC interface is inferior to the TBC of pristine GaN/SiC interface, due to the large mismatch of phonon modes between AuSn/Ti and substrates, shown as the difference of Debye temperature of two materials. Overall, we measured the TBC at interface between GaN and thermal conductive substrates, and provided a guideline for designing the interface between GaN and substrate at HEMT from a thermal management point of view.

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Characterization of the three-dimensional residual stress distribution in SiC bulk crystals by neutron diffraction

Abstract: The neutron diffraction method was adopted to study the three-dimensional residual stress distribution in SiC bulk crystals for the first time.

Cited by 19 publications

References 21 publications

Analysis of the Basal Plane Dislocation Density and Thermomechanical Stress during 100 mm PVT Growth of 4H-SiC

Analysis of the Basal Plane Dislocation Density and Thermomechanical Stress during 100 mm PVT Growth of 4H-SiC

Control of the temperature field by double induction coils for growth of large-sized SiC single crystals via the physical vapor transport technique

Reduced thermal boundary conductance in GaN-based electronic devices introduced by metal bonding layer

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