Characterization of thermal stresses and plasticity in through-silicon via structures for three-dimensional integration

Jiang, Tengfei; Ryu, Suk Kyu; Im, James S.; Huang, Rui; Ho, Paul S.

doi:10.1063/1.4881340

Cited by 5 publications

(1 citation statement)

References 33 publications

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“…To evaluate the impact of TSV structure on BEOL layers near the surface of Si, experiments have been conducted to measure the stress in the surrounding Si; eg, the local strain around TSV interconnections was characterized with X‐ray microdiffraction . The local plasticity deformation around isolated TSV was further measured by X‐ray microdiffraction, and the investigation also indicated that the magnitude of induced stress for TSV gradually decreased within a few microns, and the nearby structures surrounding TSV interconnects were affected obviously . Except for the impact of induced stress on TSV interconnects, the thermomechanical behaviours of TSV also lead to severe reliability issues on BEOL layers such as failure caused by protrusion of TSV‐Cu.…”

Section: Introductionmentioning

confidence: 99%

Optimization of TSV interconnects and BEOL layers under annealing process through fracture evaluation

Qin

Zhang

Dai

et al. 2020

Fatigue Fract Eng Mat Struct

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Through silicon via (TSV) is a crucial interconnection structure in 3-D integrated circuits. However, protrusion and intrusion of TSV-Cu caused by annealing could lead to cracking and failure of back-end-of-line (BEOL) layers and TSV interconnects due to mismatch of coefficient of thermal expansion. In this paper, optimizations of TSV interconnects and BEOL layers under annealing process are investigated based on fracture evaluation. Influences of geometrical factors including the TSV geometry dimension, the distance between TSV and BEOL layers, and pitch size of Cu via on energy release rate and J-integral are studied for TSV interconnects and BEOL layers with cracks.Effect of material properties for low k dielectrics on interfacial fracture of BEOL layers and TSV interconnects is also given. Optimized geometrical factors and optimized material properties of low k dielectrics are presented in this paper. Fracture-based method sheds a light on emerging electronic packaging optimization. K E Y W O R D Sannealing process, BEOL layer, energy release rate, J-integral, TSV interconnect

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Section: Introductionmentioning

confidence: 99%