Characterizing and Reducing the Layout Dependent Effect and Gate Resistance to Enable Multiple-Vt Scaling for a 3nm CMOS Technology

Lu, Chunte A.; Lee, H.P.; Chen, H.C.; Lin, Yung-Tao; Chung, Yong Hyun; Wang, S.H.; Yeh, J.-Y.; Chang, V.S.; Chiang, Meng-Hsueh; Chang, W.; Chung, Hyun Chul; Cheng, Chao-Ching; Hsu, Hsin-Wu; Liu, H.H.; Chen, William P.N.; Lin, Chih‐Yu

doi:10.23919/vlsitechnologyandcir57934.2023.10185282

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 2023

DOI: 10.23919/vlsitechnologyandcir57934.2023.10185282

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Characterizing and Reducing the Layout Dependent Effect and Gate Resistance to Enable Multiple-Vt Scaling for a 3nm CMOS Technology

Chunte A. Lu

H.P. Lee

H.C. Chen

et al.

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Metal Boundary Effect Mitigation by HKMG Thermal Process Optimization in FinFET Integration Technology

Li,

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Characterizing and Reducing the Layout Dependent Effect and Gate Resistance to Enable Multiple-Vt Scaling for a 3nm CMOS Technology

Cited by 1 publication

References 1 publication

Metal Boundary Effect Mitigation by HKMG Thermal Process Optimization in FinFET Integration Technology

Metal Boundary Effect Mitigation by HKMG Thermal Process Optimization in FinFET Integration Technology

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