2013 IEEE International Electron Devices Meeting 2013
DOI: 10.1109/iedm.2013.6724675
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Characterizing grain size and defect energy distribution in vertical SONOS poly-Si channels by means of a resistive network model

Abstract: The characterization of vertical poly-Si transistors, important for optimizing vertical SONOS memory configurations, is studied by means of a resistive network model. The statistical variation of the I SD -V G characteristics allows to extract the poly-Si grain size and from the sub-threshold regime information on the energy distribution of the poly-Si defects is extracted. This model indicates the separated impact of interface states and poly-Si states on current and V th . Introduction and purpose

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Cited by 14 publications
(7 citation statements)
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“…Therefore, mode-1 at low g m is grain boundary-limited, while mode-2 at high g m reflects the single-crystal value without any grain boundary obstruction. Note that the γ-value of 160 is significantly lower than the values reported in poly-Si (γ=~700) [12]. This indicates that in epi-Si, the eventual grain boundaries are less 'resistive' and could be interpreted as stacking faults or twins rather than poly-Si-like grain boundaries, as also concluded from TEM inspections (Fig.…”
Section: Resistive Network Modelmentioning
confidence: 64%
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“…Therefore, mode-1 at low g m is grain boundary-limited, while mode-2 at high g m reflects the single-crystal value without any grain boundary obstruction. Note that the γ-value of 160 is significantly lower than the values reported in poly-Si (γ=~700) [12]. This indicates that in epi-Si, the eventual grain boundaries are less 'resistive' and could be interpreted as stacking faults or twins rather than poly-Si-like grain boundaries, as also concluded from TEM inspections (Fig.…”
Section: Resistive Network Modelmentioning
confidence: 64%
“…Applying this model, we have already shown that the variance of the g m measured on a large number of identical devices increases when the average number of grains in the channel is decreased [12]. For an epi-grown device with one single grain, a distribution with very small variance would be expected, since no grain boundary-induced variability exists.…”
Section: Resistive Network Modelmentioning
confidence: 91%
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“…Several works have exploited numerical simulations to investigate the effect of grain boundaries on variability in nanowires [340][341][342][343][344][345] and 3D NAND devices [346,347]. However, several important features of such models still have to be assessed, such as the grain size [348,349], the density and energy distribution of grain boundary traps [350,351], and the mobility degradation and conduction process at the grain boundaries [352,353]. …”
Section: Polysilicon Grainsmentioning
confidence: 99%