2011 IEEE 19th Annual International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems 2011
DOI: 10.1109/mascots.2011.68
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Characterizing Memory Write References for Efficient Management of Hybrid PCM and DRAM Memory

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Cited by 44 publications
(36 citation statements)
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“…This result contradicts the analysis of desktop applications, in which frequency is much stronger than temporal locality [7]. We cannot pinpoint the exact reason but it may be due to the read-intensive memory workload characteristics of smartphone environments.…”
Section: Comparing Temporal Locality and Frequencycontrasting
confidence: 70%
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“…This result contradicts the analysis of desktop applications, in which frequency is much stronger than temporal locality [7]. We cannot pinpoint the exact reason but it may be due to the read-intensive memory workload characteristics of smartphone environments.…”
Section: Comparing Temporal Locality and Frequencycontrasting
confidence: 70%
“…This is different from memory references of desktop applications, in which a certain type of writeintensive applications exists [7]. ·Though smartphone memory references are readintensive, more than one half of memory footprints accounts for write references.…”
Section: Summary and Implicationsmentioning
confidence: 89%
“…First, we adopt high performance NVRAM such as PCM (phase-change memory) or STT-MRAM (spin torque transfer magnetic RAM) as the storage of real-time applications. Unlike flash memory, as its underlying structure does not require garbage collection but provides small and constant access latency, NVRAM ensures predictable I/O performance for real-time tasks [1], [2]. Second, we propose a dual purpose CPU scheduler, in which one core is exclusively used for a real-time job.…”
Section: Introductionmentioning
confidence: 99%
“…Phase change memory (PCM) is one of the most promising technologies for the NVRAM based memory system. However, PCM has write latencies roughly 6-10 times slower than that of DRAM [1,2]. Moreover, its lifetime is much shorter than DRAM due to the limited number of write operations allowed to each PCM cell [3].…”
Section: Introductionmentioning
confidence: 99%
“…The primary performance bottleneck in page replacement is the slow write speed of the NVRAM. Previous works mostly aim to develop efficient methods to map pages on DRAM and NVRAM [2].…”
Section: Introductionmentioning
confidence: 99%