Characterizing On-Chip Traffic Patterns in General-Purpose GPUs: A Deep Learning Approach

Li, Yunfan; Penney, Drew; Ramamurthy, Abhishek; Chen, Lizhong

doi:10.1109/iccd46524.2019.00016

“…7. However, several suggested models have considered the power of using GPUs to accelerate deep ML applications in [6,[79][80][81]. Using GPUs, DL algorithms can process data even faster than traditional NN algorithms, which require significant amounts of computing resources to run.…”

Section: Platform Acceleratormentioning

confidence: 99%

“…This allowed us to perform DL tasks such as image recognition in real time, as shown in [6]. Using the GPU framework for the classification of traffic patterns in [79], the dataset was transformed into 2D heat maps clusters, through T-distributed stochastic neighbors in that work. On the other hand, the DL technique in the form of CNN was used for feature extraction.…”

Section: Platform Acceleratormentioning

confidence: 99%

Power-aware Future Computing Systems Using Machine Learning Techniques

Al-Obaidy

2024

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0

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<p>There is a growing demand for hardware systems that are computationally efficient and energy saving, to accelerate compute-intensive applications. These exciting challenges, such as memory access and GPU throughput, take performance, power, and resource trade-offs into account. This is especially relevant to a relatively new approach: Accelerating and running parallel computing systems using a machine learning (ML) technique. The objective of this thesis is to explore the hardware design requirements, and select appropriate choices for multi-core architectures, based on different ML, to address these challenges. This thesis contributes by developing effective hardware architectures which trade-off design objectives, by focusing on the following four distinct fields: • Utilization of low-power cache designs. The objective of this design is to use the artificial neural network (ANN) predictive model to optimize a hybrid spin-torque transfer random-access memory (STT-RAM), and static random-access memory (SRAM), for multicore chips. The simulation results demonstrate that the approach can result in significant power-aware improvement for different workloads. • Development of algorithms that facilitate power savings for three-dimensional integrated networks-on-chips (3D-NoCs) design. A novel approach was efficiently developed to predict the suitable routing algorithm based on the ANN model. A trade-off power-performance function was extracted as a target for the prediction mechanism. The obtained results show high throughput with low power consumption, and reduced thermal hotspots. • Enhance power-aware resources for general purpose graphics processing unit (GPGPU). The customized model is obtained by utilizing the available chip units for each application. The energy-delay product was adopted as the target factor for the proposed ANN model. The results show that when the GPU platform is tuned to the required resources, prediction accuracy, and power consumption are highly improved. This methodology provides more flexibility for the running application to face power challenges when using maximum hardware on the GPU systems. • To improve the performance of the 3D-NoC accelerator platform, we extended the integrated 3D-NoC based ANN simulator to support interconnection routing through adding torus topology. The simulation results for the case study concluded that the modified platform contributes towards low latency and reduced power consumption, especially with respect to high NoC dimensions.</p>

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“…7. However, several suggested models have considered the power of using GPUs to accelerate deep ML applications in [6,[79][80][81]. Using GPUs, DL algorithms can process data even faster than traditional NN algorithms, which require significant amounts of computing resources to run.…”

Section: Platform Acceleratormentioning

confidence: 99%

Power-aware Future Computing Systems Using Machine Learning Techniques

Al-Obaidy

2024

Preprint

0

View full text Add to dashboard Cite

<p>There is a growing demand for hardware systems that are computationally efficient and energy saving, to accelerate compute-intensive applications. These exciting challenges, such as memory access and GPU throughput, take performance, power, and resource trade-offs into account. This is especially relevant to a relatively new approach: Accelerating and running parallel computing systems using a machine learning (ML) technique. The objective of this thesis is to explore the hardware design requirements, and select appropriate choices for multi-core architectures, based on different ML, to address these challenges. This thesis contributes by developing effective hardware architectures which trade-off design objectives, by focusing on the following four distinct fields: • Utilization of low-power cache designs. The objective of this design is to use the artificial neural network (ANN) predictive model to optimize a hybrid spin-torque transfer random-access memory (STT-RAM), and static random-access memory (SRAM), for multicore chips. The simulation results demonstrate that the approach can result in significant power-aware improvement for different workloads. • Development of algorithms that facilitate power savings for three-dimensional integrated networks-on-chips (3D-NoCs) design. A novel approach was efficiently developed to predict the suitable routing algorithm based on the ANN model. A trade-off power-performance function was extracted as a target for the prediction mechanism. The obtained results show high throughput with low power consumption, and reduced thermal hotspots. • Enhance power-aware resources for general purpose graphics processing unit (GPGPU). The customized model is obtained by utilizing the available chip units for each application. The energy-delay product was adopted as the target factor for the proposed ANN model. The results show that when the GPU platform is tuned to the required resources, prediction accuracy, and power consumption are highly improved. This methodology provides more flexibility for the running application to face power challenges when using maximum hardware on the GPU systems. • To improve the performance of the 3D-NoC accelerator platform, we extended the integrated 3D-NoC based ANN simulator to support interconnection routing through adding torus topology. The simulation results for the case study concluded that the modified platform contributes towards low latency and reduced power consumption, especially with respect to high NoC dimensions.</p>

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“…They use profiling results from earlier-generation GPUs (Haswell GT2) to train performance predictors for later/future-generation GPUs (Broadwell GT2/3, Skylake GT3), with more than 10,000 speedup compared to cycle-accurate GPU simulators. Li et al [138] reassess prevailing assumptions of GPGPU traffic patterns, and propose a scheme that combines a CNN with a t-distributed stochastic neighbor embedding to classify different traffic patterns.…”

Section: Graphics Processing Unit (Gpu)mentioning

confidence: 99%

A Survey of Machine Learning for Computer Architecture and Systems

Wu,

Xie

2021

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It has been a long time that computer architecture and systems are optimized to enable efficient execution of machine learning (ML) algorithms or models. Now, it is time to reconsider the relationship between ML and systems, and let ML transform the way that computer architecture and systems are designed. This embraces a twofold meaning: the improvement of designers' productivity, and the completion of the virtuous cycle. In this paper, we present a comprehensive review of work that applies ML for system design, which can be grouped into two major categories, ML-based modelling that involves predictions of performance metrics or some other criteria of interest, and ML-based design methodology that directly leverages ML as the design tool. For ML-based modelling, we discuss existing studies based on their target level of system, ranging from the circuit level to the architecture/system level. For ML-based design methodology, we follow a bottom-up path to review current work, with a scope of (micro-)architecture design (memory, branch prediction, NoC), coordination between architecture/system and workload (resource allocation and management, data center management, and security), compiler, and design automation. We further provide a future vision of opportunities and potential directions, and envision that applying ML for computer architecture and systems would thrive in the community. CCS Concepts: • Computing methodologies → Machine learning; • Computer systems organization → Architectures; • General and reference → Surveys and overviews.

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Characterizing On-Chip Traffic Patterns in General-Purpose GPUs: A Deep Learning Approach

Cited by 5 publications

References 22 publications

Power-aware Future Computing Systems Using Machine Learning Techniques

Power-aware Future Computing Systems Using Machine Learning Techniques

Power-aware Future Computing Systems Using Machine Learning Techniques

A Survey of Machine Learning for Computer Architecture and Systems

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