Characterizing the resource-sharing levels in the UltraSPARC T2 processor

Cakarevic, Vladimir; Radojković, Petar; Verdú, Javier; Pajuelo, Alex; Cazorla, Francisco J.; Nemirovsky, Mario; Valero, Mateo

doi:10.1145/1669112.1669173

Cited by 28 publications

(34 citation statements)

References 12 publications

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“…More recently, Eyerman et al [13] studied job symbiosis and proposed a model to predict whether jobs create positive or negative symbiosis when co-scheduled without actually running the co-schedule. Concerning SMT multicores,Čakarević et al [14] characterized different types of resource sharing in an UltraSPARC T2 processor and improved the execution of multithreaded applications with a resource sharing aware scheduler. Acosta et al [15] showed that processor throughput is highly dependent on thread allocation and proposed an allocation policy that combines computation and memory bounded processes in each core.…”

Section: Related Workmentioning

confidence: 99%

Bandwidth-Aware On-Line Scheduling in SMT Multicores

Feliu

Sahuquillo

Petit

et al. 2016

IEEE Trans. Comput.

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Section: Related Workmentioning

confidence: 99%

Bandwidth-Aware On-Line Scheduling in SMT Multicores

Feliu

Sahuquillo

Petit

et al. 2016

IEEE Trans. Comput.

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“…Cakarevic et al [23] use a similar set of micro benchmarks as Doucette and Fedorova to characterize the shared hardware resource in UltraSPARC T2. They co-run their micro benchmarks, stressing different shared resources, and investigate how the micro benchmarks impact each other.…”

Section: Related Workmentioning

confidence: 99%

Cache Pirating: Measuring the Curse of the Shared Cache

Eklov

Nikoleris

Black-Schaffer

et al. 2011

2011 International Conference on Parallel Processing

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We present a low-overhead method for accurately measuring application performance (CPI) and off-chip bandwidth (GB/s) as a function of its the available shared cache capacity, on real hardware, with no modifications to the application or operating system. We accomplish this by co-running a Pirate application that "steals" cache space with the Target application. By adjusting how much space the Pirate steals during the Target's execution, and using hardware performance counters to record the Target's performance, we can accurately and efficiently capture performance data for the Target application as a function of its available shared cache. At the same time we use performance counters to monitor the Pirate to ensure that it is successfully stealing the desired amount of cache.To evaluate this approach, we show that 1) the cache available to the Target behaves as expected, 2) the Pirate steals the desired amount of cache, and 3) the Pirate does not impact the Target's performance. As a result, we are able to accurately measure the Target's performance while stealing between 0MB and an average of 6.1MB of the 8MB of cache on our Nehalem based test system with an average measurement overhead of only 5.5%.

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“…Multithreaded processors 1 are comprised of several cores executing threads that share resources at multiple levels [57]. For example, in a CMP processor where each core supports concurrent execution of several threads through SMT, all simultaneously running threads share global resources such as the last level of cache and the I/O.…”

Section: Introductionmentioning

confidence: 99%

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach

Radojković

Carpenter

Moretó

et al. 2016

IEEE Trans. Comput.

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Abstract-The introduction of multicore/multithreaded processors, comprised of a large number of hardware contexts (virtual CPUs) that share resources at multiple levels, has made process scheduling, in particular assignment of running threads to available hardware contexts, an important aspect of system performance. Nevertheless, thread assignment of applications running on state-of-the art processors is an NP-complete problem. Over the years, numerous studies have proposed heuristic-based algorithms for thread assignment. Since the thread assignment problem is intractable, it is in general impossible to know the performance of the optimal assignment, so the room for improvement of a given algorithm is also unknown. It is therefore hard to decide whether to invest more effort and time to improve an algorithm that may already be close to optimal. In this paper, we present a statistical approach to the thread assignment problem. First, we present a method that predicts the performance of the optimal thread assignment, based on the observed performance of each thread assignment in a random sample. The method is based on Extreme Value Theory (EVT), a branch of statistics that analyses extreme deviations from the population mean. We also propose sample pruning, a method that significantly reduces the time required to apply the statistical method by reducing the number of candidate solutions that need to be measured. Finally, we show that, if no suitable heuristicbased algorithm is available, a sample of several thousand random thread assignments is enough to obtain, with high confidence, an assignment with performance close to optimal. The presented approach is architecture and application independent, and it can be used to address the thread assignment problem in various domains. It is especially well suited for systems in which the workload seldom changes. An example is network systems, which typically provide a constant set of services that are known in advance, with network applications performing a similar processing algorithm for each packet in the system. In this paper, we validate our methods with an industrial case study for a set of multithreaded network applications on an UltraSPARC T2 processor. This article is an extension of our previous work [44], which was published in

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Characterizing the resource-sharing levels in the UltraSPARC T2 processor

Cited by 28 publications

References 12 publications

Bandwidth-Aware On-Line Scheduling in SMT Multicores

Bandwidth-Aware On-Line Scheduling in SMT Multicores

Cache Pirating: Measuring the Curse of the Shared Cache

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach

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