Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect

Aarestad, Jim; Lamech, Charles; Plusquellic, Jim; Acharyya, Dhruva; Agarwal, Kanak

doi:10.1145/2024724.2024848

Cited by 7 publications

(3 citation statements)

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“…Though repeating measurement can reduce these errors [27], the delays of selected paths can still not be obtained accurately [16], [18], [27]. Hence, the fitting errors are further evaluated when measurement errors with Gaussian distribution (SD ≈ 1.6%) exist.…”

Section: Fitting Errorsmentioning

confidence: 99%

LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization

Shi

et al. 2017

IEICE Trans. Inf. & Syst.

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SUMMARYProcess variation has become prominent in the advanced CMOS technology, making the timing of fabricated circuits more uncertain. In this paper, we propose a Layout-Aware Path Selection (LAPS) technique to accurately estimate the circuit timing variation from a small set of paths. Three features of paths are considered during the path selection. Experiments conducted on benchmark circuits with process variation simulated with VARIUS show that, by selecting only hundreds of paths, the fitting errors of timing distribution are kept below 5.3% when both spatial correlated and spatial uncorrelated process variations exist.

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Section: Fitting Errorsmentioning

confidence: 99%

LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization

Shi

et al. 2017

IEICE Trans. Inf. & Syst.

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“…It has been shown that the frequency variation can be as much as 30% and up to 20x variations in chip leakage power for a processor designed in 180nm technology [9]. Based on a test structure fabricated in IBM's 65 nm Silicon-On-Insulator (SOI) technology, Aarestad et al [10] showed that worst case delay variations caused by chip-to-chip process variations can be as large as 21%. As design parameters of processing cores deviate from their nominal values, the system design objectives can be severely compromised, or even worse, a computing system can malfunction or even fail.…”

Section: Introductionmentioning

confidence: 99%

Topology Virtualization for Throughput Maximization on Many-Core Platforms

Wang

Quan

Ren

et al. 2012

2012 IEEE 18th International Conference on Parallel and Distributed Systems

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As transistor's feature size continues to scale down into the deep sub-micron domain, IC chip performance variation caused by manufacturing process becomes un-negligible and can cause significant discrepancies between an application's nominal design and its actual realization on individual manycore platforms. In this paper, we study the problem on how to reduce the total schedule length of a task graph when realizing its nominal design on individual Network-on-Chip(NoC) based many-core platform with faulty cores. Different from traditional approaches to re-define the mapping/scheduling decisions in the nominal design, our methods judiciously mirror the physical architecture of each individual platform to the logical platform, based on which the nominal design is conducted. To facilitate the phyical/logic architecture virtualization, we develop a performance metric based on the opportunity cost, a concept borrowed from the economics field. Three virtualization heuristics are presented in this paper. Our experimental results show that the proposed approach can achieve up to 30% with an average 15% performance improvement by taking advantage of the heterogeneity of each individual platform.

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“…It has been shown that the frequency variation can be as much as 30% and up to 20x variations in chip leakage power for a processor designed in 180nm technology [24]. Based on a test structure fabricated in IBM's 65 nm Silicon-On-Insulator (SOI) technology, Aarestad et al [3] showed that worst case delay variations caused by chip-to-chip process variations can be as large as 21%. As design parameters of processing cores deviate from their nominal values, the system design objectives can be severely compromised, or even worse, a computing system can malfunction or even fail.…”

Section: Related Workmentioning

confidence: 99%

On the Design of Real-Time Systems on Multi-Core Platforms under Uncertainty

Wang¹

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To ensure timing constraints, traditional real-time system designs usually adopt a worst-case based deterministic approach. However, such an approach is becoming out of sync with the continuous evolution of IC technology and increased complexity of real-time applications. As IC technology continues to evolve into the deep submicron domain, process variation causes processor performance to vary from die to die, chip to chip, and even core to core. The extensive resource sharing on multicore platforms also significantly increases the uncertainty when executing real-time tasks. The traditional approach can only lead to extremely pessimistic, and thus, unpractical design of real-time systems.Our research seeks to address the uncertainty problem when designing real-time systems on multi-core platforms. We first attacked the uncertainty problem caused by process variation. We proposed a virtualization framework and developed techniques to optimize the system's performance under process variation. We further studied the problem on peak temperature minimization for real-time applications on multi-core platforms. Three heuristics were developed to reduce the peak temperature for real-time systems. Next, we sought to address the uncertainty problem vi in real-time task execution times by developing statistical real-time scheduling techniques. We studied the problem of fixed-priority real-time scheduling of implicit periodic tasks with probabilistic execution times on multi-core platforms. We further extended our research for tasks with explicit deadlines. We introduced the concept of harmonic to a more general task set, i.e. tasks with explicit deadlines, and developed new task partitioning techniques. Throughout our research, we have conducted extensive simulations to study the effectiveness and efficiency of our developed techniques.The increasing process variation and the ever-increasing scale and complexity of real-time systems both demand a paradigm shift in the design of real-time applications. Effectively dealing with the uncertainty in design of real-time applications is a challenging but also critical problem. Our research is such an effort in this endeavor, and we conclude this dissertation with discussions of potential future work.

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Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect

Cited by 7 publications

References 10 publications

LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization

LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization

Topology Virtualization for Throughput Maximization on Many-Core Platforms

On the Design of Real-Time Systems on Multi-Core Platforms under Uncertainty

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