Charge diffusion in silicon nitrides: Scalability assessment of nitride based flash memory

Abstract

Electron and hole diffusion coefficients of stoichiometric silicon nitride, silicon rich nitride, and silicon oxynitride were evaluated from variable temperature electrostatic force microscopy (EFM) analysis. Among them, stoichiometric silicon nitride is shown to have smallest diffusion coefficient although silicon oxynitride has the higher temperature activation energy. Scaling charge trap flash towards sub-20nm regime should be accompanied by hole dispersion management, minimization of internal electric field, and adjustment of retention specification.

Visualization on charge distribution behavior in thickness-scalable HfO<inf>2</inf> trapping layer by in-situ electron holography and Kelvin Probe Force Microscopy technology

“…lateral diffusion coefficients are extracted by fitting with the equation (1), where p, U, D, t and x is charge density, constant related to initial charge density, diffusion coefficient, elapsed time and lateral dimension, respectively. 5 Fitting results are about 1.1520*10 -14 , 2.0541*10 -14 and 4.8512*10 -14 (unit: cm 2 /s) corresponding to samples S1, S3 and S5. Fig.6 presents the CPD decay profile of sample S5 measured at 80 o C and 120 o C, which apparently shows that CPD decay becomes more severe with elevated temperature.…”

In situ electron holography study of charge distribution in high-κ charge-trapping memory

“…Ramanathan et al 9 noted that the C-V curve could not perfectly reflect the chargetrapping phenomena because of the complexity of test environment. Recently, several types of scanning probe microscopy (SPM), such as electrostatic force microscope 10 , Kelvin force microscope 11 , scanning capacitance microscope 12 and conductive atomic force microscope 13 , have been used to profile the charge distribution in CTM with tens of nanometre resolution. SPM can track the lateral charge map and diffusion process but the working mode and the limited spatial resolution impede it to distinguish the vertical location of the trapped charges, which have an impact significantly on the performance of the device.…”

Effect of Lateral Charge Diffusion on Retention Characteristics of 3D NAND Flash Cells

“…When V th is positive after the erase operation with a low erase bias, the number of electrons and holes remaining in the IGS region seems to be different from that in the previous work [3], [9]. The electrons in the IGS region, opposite to the holes, slow down lateral diffusion and reduce V th [4], [6], [7], [9], [12]. Therefore, this result can be interpreted as the result of further reducing the lateral diffusion by increasing the number of electrons and reducing the number of holes in the IGS region.…”

“…On the other hand, since the V th of adjacent cells is different from that of n th cell, lateral diffusion occurs. Holes injected into the nitride layer during erase operation also cause lateral diffusion [12]. Therefore, we can investigate the effect of lateral diffusion while changing erase bias in Procedure 1.…”