2000
DOI: 10.1063/1.1328101
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Charge storage and interface states effects in Si-nanocrystal memory obtained using low-energy Si+ implantation and annealing

Abstract: Thin SiO2 oxides implanted by very-low-energy (1 keV) Si ions and subsequently annealed are explored with regards to their potential as active elements of memory devices. Charge storage effects as a function of Si fluence are investigated through capacitance and channel current measurements. Capacitance–voltage and source–drain current versus gate voltage characteristics of devices implanted with a dose of 1×1016 cm−2 or lower exhibit clear hysteresis characteristics at low electric field. The observed fluence… Show more

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Cited by 142 publications
(79 citation statements)
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“…However, floating-gate based flash memory has been reported to have limits in continuous device scaling due to increasing cell-to-cell interference, decreasing coupling ratio, non-scalable tunnelling oxide thickness, decreasing tolerance for charge loss, etc. Therefore, active research has been performed on flash memory devices with discrete charge trapping layers, such as silicon-oxide-nitride-oxide-silicon (SONOS) devices [29][30][31][32][33]25] or nanocrystal (NC)-based memory devices (nano-floating gate memory devices) [34][35][36][37][38]. Because of their better endurance, smaller chip size, and lower power consumption when compared with floating-gate devices, this technology is of great interest to the electronics industry.…”
Section: Introductionmentioning
confidence: 99%
“…However, floating-gate based flash memory has been reported to have limits in continuous device scaling due to increasing cell-to-cell interference, decreasing coupling ratio, non-scalable tunnelling oxide thickness, decreasing tolerance for charge loss, etc. Therefore, active research has been performed on flash memory devices with discrete charge trapping layers, such as silicon-oxide-nitride-oxide-silicon (SONOS) devices [29][30][31][32][33]25] or nanocrystal (NC)-based memory devices (nano-floating gate memory devices) [34][35][36][37][38]. Because of their better endurance, smaller chip size, and lower power consumption when compared with floating-gate devices, this technology is of great interest to the electronics industry.…”
Section: Introductionmentioning
confidence: 99%
“…2) Low-Energy Si Implantation: This method involves Si ion implantation into a bare oxide layer on Si substrates [6], [7], which produces a Si excess in the oxide. Subsequent high-temperature annealing drives the and Si phase separation.…”
mentioning
confidence: 99%
“…These crystal shapes have also been investigated by Monte Carlo simulations [53]. Size distributions are narrower than for compound nanocrystals formed by ion implantation, and can be further narrowed (or involve the formation of platelet structures) by using low-energy implants, as has been done for silicon-nanocrystal-based nonvolatile memory devices [54,55].…”
Section: Light-emitting Materialsmentioning
confidence: 99%