Charge Trapping Mechanism Leading to Sub-60-mV/decade-Swing FETs

Abstract

(2017) Charge trapping mechanism leading to sub-60-mV/decade-Swing FETs. IEEE Transactions on Electron Devices, 64 (7). pp. 2789 -2796 This version is available from Sussex Research Online: http://sro.sussex.ac.uk/68771/ This document is made available in accordance with publisher policies and may differ from the published version or from the version of record. If you wish to cite this item you are advised to consult the publisher's version. Please see the URL above for details on accessing the published version. Copyright and reuse:Sussex Research Online is a digital repository of the research output of the University.Copyright and all moral rights to the version of the paper presented here belong to the individual author(s) and/or other copyright owners. To the extent reasonable and practicable, the material made available in SRO has been checked for eligibility before being made available.Copies of full text items generally can be reproduced, displayed or performed and given to third parties in any format or medium for personal research or study, educational, or not-for-profit purposes without prior permission or charge, provided that the authors, title and full bibliographic details are credited, a hyperlink and/or URL is given for the original metadata page and the content is not changed in any way. Abstract-In this work, we present a novel method to reduce the subthreshold swing of field-effect transistors below 60 mV/dec. Through modeling, we directly relate trap charge movement between the gate electrode and the gate dielectric to subthreshold swing reduction. We experimentally investigate the impact of charge exchange between a Cu gate electrode and a 5 nm thick amorphous Al2O3 gate dielectric in an InGaZnO4 thin-film transistor. Positive trap charges are generated inside the gate dielectric while the semiconductor is in accumulation. During the subsequent de-trapping, the subthreshold swing diminishes to a minimum value of 46 mV/dec at room temperature. Furthermore, we relate the charge trapping/de-trapping effects to a negative capacitance behavior of the Cu/Al2O3 metal-insulator structure. IEEE TRANSACTIONS ON ELECTRON DEVICES

Ferroelectric‐Like Charge Trapping Thin‐Film Transistors and Their Evaluation as Memories and Synaptic Devices

“…The TFT shows counter‐clockwise hysteresis in I D , which confirms positive charges within the Al 2 O 3 gate dielectric. Its V GS back sweep subthreshold swing is reduced below 60 mV per decade from charge detrapping thereby demonstrating its low‐power capability. These features also indicate a ferroelectric‐like charge trapping behavior in the TFTs as both the counter‐clockwise I D hysteresis and the sub‐60 mV per decade subthreshold swing can be found in field‐effect transistors with ferroelectric gate insulators .…”

Half-volt operation of IGZO thin-film transistors enabled by ultrathin HfO2 gate dielectric

“…Researchers have showed that the properties of ultrathin gate dielectrics may be different from thick ones. 25,26 The accurate value of gate dielectric capacitance (Cox) plays a vital part in the calculation of carrier mobility and interface trap density (Nt), and thus MIS capacitors were made to confirm the capacitance of the thin HfO2 layer. Figure 2(a) and the inset show the C-V characteristics and schematic cross-sectional view of an Al/HfO2 (5 nm)/p-Si capacitor, respectively.…”

“…However, very thin gate dielectrics have been found to show different dielectric properties from thick ones. 19,25,26 So, it is worth exploring the characteristics of devices based on ultrathin high-materials.…”

Optoelectronic In‐Ga‐Zn‐O Memtransistors for Artificial Vision System

“…By adjusting the Fermi level of the gate metal, the trap state in the Al 2 O 3 layer required for charge exchange can be filled or cleared. [30,31] The charge carriers trapped by the Al 2 O 3 layer produce a trap charge voltage, which generates an indirect capacitive interaction with the semiconductor channel via the ion gel. Under the influence of the electric field, the formation of electric double layer in ion gel affords a large specific capacitance of 4.31 µF cm −2 .…”

“…[27,28] It was found that an oxide transistor with charge capture can provide a large hysteresis window. [29][30][31] Such devices can provide an excellent charge trapping and memory behavior, which facilitates their application as a memristive device. If the channel layer of such transistors exhibits a strong photoresponse, then neuroplasticity can be induced by photogenerated charge trapping through photonic stimuli and gate voltage (V gs ) modulation, thus permitting the simulation of visual functions.…”