Charge trapping related channel modulation instability in P-GaN gate HEMTs

Li, Xueyang; Xie, Gang; Tang, Cen; Sheng, Kuang

doi:10.1016/j.microrel.2016.07.040

Cited by 17 publications

(4 citation statements)

References 17 publications

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“…The heat diffusion from the hotspot generated at the gate and the thermal trend expected for the Schottky contact and the pnjunction, explain the gate current increase. This would induce also a decrease of the threshold voltage (V TH ) with temperature [24]. This assumption agrees with experimental results of V TH negative temperature dependence on these devices, as shown in figure 5.…”

Section: Short Circuit Behavioursupporting

confidence: 92%

Unstable behaviour of normally-off GaN E-HEMT under short-circuit

Martínez

Maset

Sanchis-Kilders

et al. 2018

Semicond. Sci. Technol.

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The short-circuit capability of power switching devices plays an important role in fault detection and the protection of power circuits. In this work, an experimental study on the short-circuit (SC) capability of commercial 600 V Gallium Nitride enhancement-mode high-electron-mobility transistors (E-HEMT) is presented. A different failure mechanism has been identified for commercial p-doped GaN gate (p-GaN) HEMT and metal-insulator-semiconductor (MIS) HEMT. In addition to the well known thermal breakdown, a premature breakdown is shown on both GaN HEMTs, triggered by hot electron trapping at the surface, which demonstrates that current commercial GaN HEMTs has requirements for improving their SC ruggedness.

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Section: Short Circuit Behavioursupporting

confidence: 92%

Unstable behaviour of normally-off GaN E-HEMT under short-circuit

Martínez

Maset

Sanchis-Kilders

et al. 2018

Semicond. Sci. Technol.

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“…As a consequence, leakage current can slowly increase again, and threshold voltage shows an almost complete recovery, thanks to the de-trapping of holes from the p-GaN/AlGaN interface [10]. It is worth noticing that also defect generation/electron trapping in the AlGaN [11], [12], at the AlGaN/GaN interface [13], or in the buffer may lead to the observed behavior.…”

Section: B Results Of Step-stress Experiments: Three Regimes Are Observedmentioning

confidence: 90%

Degradation Mechanisms of GaN HEMTs With p-Type Gate Under Forward Gate Bias Overstress

Ruzzarin

Meneghini

Barbato

et al. 2018

IEEE Trans. Electron Devices

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This paper investigates the degradation of GaN-based HEMTs with p-type gate submitted to positive gate bias stress. Based on combined electrical and optical testing, we demonstrate the existence of different degradation processes, depending on the applied stress voltage V Gstress : 1) for V Gstress < 7 V, no significant degradation is observed, thus demonstrating a good stability of the analyzed technology; 2) for 7 V < V Gstress < 11.5 V, a negative shift in threshold voltage (V th ) is observed, well correlated with a decrease in the gate leakage current and of the luminescence signal associated with hole injection. The negative V th shift is ascribed to the trapping of holes in the AlGaN and/or p-GaN/AlGaN interface; and 3) for V Gstress ≥ 12 V, threshold voltage recovers its initial value. This is ascribed to a net-negative charge, generated either by the trapping of electrons injected from the 2-D electron gas to the AlGaN or to the de-trapping of the holes injected in 2). The results described within this paper provide relevant information for understanding the degradation dynamics of normally off GaN transistors submitted to extremely high gate voltage levels far beyond maximum use.

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“…Usually the surface traps are considered to be causes of gate lag, and the buffer traps are considered to be causes of drain lag . The analysis of the trapping phenomena in GaN‐based HEMTs has focused on the traps at the surface or in the AlGaN barrier layer . More recently, there has been growing interest in the use of an intentionally iron‐doped GaN buffer layer toward improving the performance of GaN‐based HEMTs .…”

Section: Introductionmentioning

confidence: 99%

Effects of the Trap Level in the Unintentionally Doped GaN Buffer Layer on Optimized p‐GaN Gate AlGaN/GaN HEMTs

Cai

Zhang³

et al. 2017

Physica Status Solidi (a)

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This research investigates the impacts of the AlGaN barrier layer thickness and the Al mole fraction on p‐GaN gate AlGaN/GaN HEMTs and presents an optimized structure. Based on 2‐D drift‐diffusion simulation, the effects of the trap level in the UID GaN buffer layer on the transfer and output characteristics of the optimized device are described. The energies of the trap levels are set at 0.28, 0.33, 0.4, 0.58, and 0.9 eV below the conduction band minimum, respectively. The depth of the trap level is found to influence the off‐state leakage current and on‐state ID,max. The Shockley–Read–Hall recombination model for a single trap level is used to analyze the impact of different trap levels in the UID GaN buffer on p‐GaN gate AlGaN/GaN HEMTs.

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Charge trapping related channel modulation instability in P-GaN gate HEMTs

Cited by 17 publications

References 17 publications

Unstable behaviour of normally-off GaN E-HEMT under short-circuit

Unstable behaviour of normally-off GaN E-HEMT under short-circuit

Degradation Mechanisms of GaN HEMTs With p-Type Gate Under Forward Gate Bias Overstress

Effects of the Trap Level in the Unintentionally Doped GaN Buffer Layer on Optimized p‐GaN Gate AlGaN/GaN HEMTs

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