CHARM: A checkpoint-based resource management framework for reliable multicore computing in the dark silicon era

Raparti, Venkata Yaswanth; Kapadia, Nishit; Pasricha, Sudeep

doi:10.1109/iccd.2016.7753281

Cited by 5 publications

(1 citation statement)

References 22 publications

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“…These studies of the communication barrier were conducted using the flooding protocol, which surely consumes communication resources in high quantities but is probably the most efficient protocol to discover the existence of routes. Discovering routes with adaptive routing protocols (which are much less resource demanding; e.g., see [39,40]) is of interest but cannot push away the communication barrier.…”

Section: Limit Of Stapmentioning

confidence: 99%

Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs

Louri

Collet²,

Kodi

2019

J. Emerg. Technol. Comput. Syst.

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We study the ultimate limits of hardware solutions for the self-protection strategies against permanent faults in networks on chips (NoCs). NoCs reliability is improved by replacing each base router by an augmented router which includes extra protection circuitry. We compare the protection achieved by the self-test and selfprotect (STAP) architectures to that of triple modular redundancy with voting (TMR). Two STAP architectures are considered. In the first one, a defective router self-disconnects from the network, while it self-heals in the second one. In practice, none of the considered architectures (STAP or TMR) can tolerate all the permanent faults, especially faults in the extra-circuitry for protection or voting, and consequently, there will always be some unidentified defective augmented routers which are going to transmit errors in an unpredictable manner. This study consists of tackling this fundamental problem. Specifically, we study and determine the average percentage of residual unidentified defective routers (UDRs) and their impact on the overall reliability of the NoC in light of self-protection strategies. Our study shows that TMR is the most efficient solution to limit the average percentage of UDRs when there are typically less than a 0.1 percent of defective base routers. However, TMR is also the most cost prohibitive and the least power efficient. Above 1% of defective base routers, the STAP approaches are more efficient although the protection efficiency decreases inexorably in the very defective technologies (e.g. when there is 10% or more of defective base routers). For instance, if the chip includes 10% of defective base routers, our study shows that there will remain on the average 1% of UDRs, which causes a major challenge for NoC reliability.

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Section: Limit Of Stapmentioning

confidence: 99%