Checking equivalence of quantum circuits and states

Viamontes,; Hayes,

doi:10.1109/iccad.2007.4397246

Cited by 70 publications

(48 citation statements)

References 25 publications

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“…In recent days, research in the area of reversible logic has been intensified and accelerated by the promising results. As a result, besides verification [11][12][13], testing [14][15][16], simulation [17,18], optimization [19], and debugging [20] and synthesis of reversible circuits [7], approaches exploiting permutations and truth tables [21] are main research areas. Minimizing the number of garbage outputs and number of gates are the major concerns in reversible logic circuits and it is observed that proposed 4 input ALG gate achieves minimum garbage output and leading to high speed and low power reversible circuits.…”

Section: Related Workmentioning

confidence: 99%

Reversible Arithmetic Logic Gate (ALG) for Quantum Computation

Arun

Saravanan²

2013

IJIES

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At present, Boolean algebra based computations by the use of silicon based semiconductor technology are irreversible in nature. This is due to the mismatch of number of inputs and outputs. Reversible logic circuit maps unique input to the output and ensure one to one mapping and basis for emerging applications like low-power design, quantum computation, optical computing, bioinformatics and nanotechnologies. In computing paradigm, Arithmetic Logic Unit (ALU) is one of the computing intensive building blocks of the computer that performs arithmetic and logical operations. This work understands and nurtures the necessity of reversible ALU for future revolutionary computing technologies. In this paper, a 4x4 reversible gate which alone performs arithmetic and logic operations is proposed and compared with other reversible gates like TSG, HNG and MKG, in terms of quantum cost, I/O lines and Taffoli gates. The results of different synthesis methods of 4x4 ALG using Revkit tool are studied. Proposed gate performs better than existing methods and ensures maximum logical operations like full adder, full subtractor and all logical operations with less hardware cost where other existing gates are not viable.

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Section: Related Workmentioning

confidence: 99%

Reversible Arithmetic Logic Gate (ALG) for Quantum Computation

Arun

Saravanan²

2013

IJIES

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“…[9], [10]), verification (see e.g. [11], [12], [13]), and debugging (see e.g. [14]) have been introduced.…”

Section: Introductionmentioning

confidence: 99%

Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits

Wille

Zhang

Drechsler

2013

2013 IEEE 43rd International Symposium on Multiple-Valued Logic

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Abstract-Reversible circuits are an attractive computation alternative as they build the basis for many emerging technologies such as quantum computation or low power design. Since first physical realizations of reversible circuits have already been presented in the past, how to efficiently test such circuits became a current research topic. Consequently, several approaches for Automatic Test Pattern Generation (ATPG) have been presented in the past.However, the order in which the respective faults are targeted has a significant effect on the resulting test size. While determining good fault orderings has intensely been considered for the test of conventional circuits, according strategies for reversible circuits have not been evaluated yet. This is done in this paper. To this end, a fault ordering scheme is presented that explicitely exploits the reversibility of the underlying circuits. Experimental results show that the proposed scheme leads to improvements of up to 65% in the size of the testset.

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“…[5], [6], [7], [8], [9], [10], [11], [12]). Furthermore, simulation [13], [14], optimization [15], [16], testing [17], [18], [19], and verification [20], [21] have also been investigated. However, to the best of our knowledge the problem of debugging has not been considered yet.…”

Section: Introductionmentioning

confidence: 99%

Debugging of Toffoli networks

Wille

Grosse²,

Frehse³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Intensive research is performed to find post-CMOS technologies. A very promising direction based on reversible logic are quantum computers. While in the domain of reversible logic synthesis, testing, and verification have been investigated, debugging of reversible circuits has not yet been considered. The goal of debugging is to determine gates of an erroneous circuit that explain the observed incorrect behavior.In this paper we propose the first approach for automatic debugging of reversible Toffoli networks. Our method uses a formulation for the debugging problem based on Boolean satisfiability. We show the differences to classical (irreversible) debugging and present theoretical results. These are used to speed-up the debugging approach as well as to improve the resulting quality. Our method is able to find and to correct single errors automatically.

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Checking equivalence of quantum circuits and states

Cited by 70 publications

References 25 publications

Reversible Arithmetic Logic Gate (ALG) for Quantum Computation

Reversible Arithmetic Logic Gate (ALG) for Quantum Computation

Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits

Debugging of Toffoli networks

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