Thin-®lm device processing relies heavily on the integration of a variety of materials and a wide array of process steps. These include in some instances, the integration of wet' (chemical etching) and`dry' (deposition and plasma etching) process steps. As substrates are stepped through the process sequence, there are many surfaces that ultimately become interfaces that can have a dramatic impact on ultimate device performance. However, in thin-®lm R&D, these issues are not always carefully considered. This can have severe consequences when adapting an R&D-developed process into pilot production, and ®nally, into manufacturing. In this paper, we explore the impact of process integration issues on the microstructure and device performance for three prominent photovoltaic thin-®lm technologies (cadmium telluride, copper indium diselenide, and amorphous silicon). We also consider the impact of these concepts on future research directions in thin-®lm photovoltaics.