Chemical topography analyses of silicon gates etched in HBr/Cl2/O2 and HBr/Cl2/O2/CF4 high density plasmas

Vallier, L.; Foucher, J.; Detter, X.; Pargon, E.; Joubert, O.; Cunge, G.; Lill, Thorsten

doi:10.1116/1.1563255

Cited by 26 publications

(20 citation statements)

References 13 publications

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“…The depositing plasma has been characterized by optical absorption spectroscopy and mass spectrometry and the silicon gate sidewalls composition was deduced from XPS measurements. It was shown that the passivation layers deposited on the gate sidewalls are Cl-rich silicon oxychloride layers, and that the layer deposition is oxygen-limited [17] under our conditions. The chemical composition of the layer deposited on the reactors walls was then characterized by using OES and MS during the removal of this layer by an Ar/SF 6 plasma.…”

Section: Discussionmentioning

confidence: 91%

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Correlation and Interaction between Sidewall Passivation and Chamber Walls Deposition During Silicon Gate Etching

Kogelschatz

Cunge

Joubert

et al. 2004

Contrib. Plasma Phys.

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The aim of the present paper is to review our work on plasma-surface interactions during the etching of silicon gates in low pressure high density HBr/Cl2/O2 based plasmas. In integrated circuit manufacturing, the transfer of patterns onto the polysilicon layer relies on the formation of a passivation layer on sidewalls of the etched features, which protects the silicon gate sidewall from isotropic etching. At the same time, a layer with an almost identical chemical composition is also deposited on the reactor walls and can modify the process parameters by changing the radicals' surface loss probability. In this work we use a new "plasma etching-sputtering" diagnostic technique, involving a subsequent "mild etching" of the layer deposited on the chamber walls by a few % SF6-containing Ar plasma. Thus we investigate the chemical composition of this layer. This chemical composition is deduced from the time variation of the gas phase concentration of different atoms and radicals, the etch products of the wall deposited layer, monitored during the "mild etching" of the layer by time-resolved optical emission spectroscopy and mass spectrometry.Optical absorption spectroscopy and mass spectrometry have been employed to characterize the HBr/Cl2/O2 plasma, currently used for the gate etching, and to estimate the absolute flux of neutral and ionic deposition precursors reaching the reactor walls. It comes out that the silicon wafer etch byproducts, SiClx radicals (x<2) and SiOyCl + x ions, are the main depositing agents. Finally, the chemical topography analysis method, based on the X-ray photoelectron spectroscopy, has been used to determine the chemical composition of the layer formed on the sidewalls of the silicon etched features.We show that the layers deposited on the sidewalls and on the chamber walls are both silicon oxyhalogenides (SiOyClx) compounds, formed by the subsequent oxidation of the deposited silicon chloride etching by-products.

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Section: Discussionmentioning

confidence: 91%

“…The XPS chemical topography analysis [17] then provides the chemical composition of the passivation layer deposited on the feature sidewalls during etching without air exposure (quasi in-situ).…”

Section: Experimental Set-upmentioning

confidence: 99%

Correlation and Interaction between Sidewall Passivation and Chamber Walls Deposition During Silicon Gate Etching

Kogelschatz

Cunge

Joubert

et al. 2004

Contrib. Plasma Phys.

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“…The a-C organic mask is a thick PECVD carbon-based layer and the (Si-ARC) is a thin spin coated silicon containing polymer. 26,27 Finally, the surface roughness of the sample is analyzed by ex situ AFM measurements (see Martin and Cunge for details 11 ). The development of the etching processes (random copolymer removal, hard mask opening and silicon etching) are performed in an industrial etcher (DPS TM from Applied Materials (AMAT) for 200 mm diameter wafers) that has been described elsewhere.…”

Section: Methodsmentioning

confidence: 99%

Development of plasma etching processes to pattern sub-15 nm features with PS-b-PMMA block copolymer masks: Application to advanced CMOS technology

Delalande

Cunge

Chevolleau

et al. 2014

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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Pattern transfer using poly(styrene-block-methyl methacrylate) copolymer films and reactive ion etchingThe best strategies to transfer nanoholes formed from the self-assembly of Polystyren/ Polymethylmethacrylate (PS/PMMA) based block copolymers into a silicon substrate are investigated. The authors show that specific issues are associated with the plasma etching of materials through the PS masks obtained from self-assembly. Indeed, due to the nanometric size of sub-15 nm contact holes and to their inherently high aspect ratio (>5), plasma etching processes typically used to etch SiO 2 and silicon in the microelectronic industry must be revisited. In particular, processes where the etching anisotropy relies on the formation of passivation layer on the feature's sidewalls are not adapted to nanometric dimensions because these layers tend to fill the holes leading to etch stop issues. At the same time, the ion bombarding energy must be increased as compared to a typical process to overcome differential charging effects in high aspect-ratio nanoholes. However, by developing appropriate processes-such as synchronized pulsed plasmas-the authors show that it is possible to etch 70 nm deep holes into silicon by using block copolymers and a hard mask strategy. Another interesting observation resulting from these experiments is that for sub-15 nm holes, a critical dimension (CD)-dispersion of few nm leads to strong aspect ratio dependent etch rates. In addition, a careful analysis of the dispersion of the holes' CD after each plasma steps shows that the CD control is far from satisfying advanced CMOS technology requirements. A critical issue comes from the uncompleted PMMA removal from the PS/PMMA matrix during our self-assembly process: variable amount of PMMA remains in the PS holes, leading to microloading effects during the etching steps, which in turn generates CD-control loss. This problem perhaps can be solved by combining UV exposure to acetic acid treatment to provide PS masks free of PMMA residues before plasma etching.

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“…The silicon gate etch process has also been studied by Joubert and co-workers in a series of papers. [4][5][6][7][8][9][10][11] Their studies bring to light the complex interrelationships of process chemistry, feature layout ͑pitch and CD͒, and chamber condition. Vallier et al 6 use x-ray photoemission spectroscopy ͑XPS͒ measurements to show that the fluorine from CF 4 can generate volatile etch products from the sidewall ͑SiOF͒ that may be recycled to the silicon sidewalls impacting profile.…”

Section: Introductionmentioning

confidence: 99%

“…[4][5][6][7][8][9][10][11] Their studies bring to light the complex interrelationships of process chemistry, feature layout ͑pitch and CD͒, and chamber condition. Vallier et al 6 use x-ray photoemission spectroscopy ͑XPS͒ measurements to show that the fluorine from CF 4 can generate volatile etch products from the sidewall ͑SiOF͒ that may be recycled to the silicon sidewalls impacting profile. Detter et al 10 have shown that oxygen addition, in turn, produces COF and COF 2 products leaching CF x from the sidewalls, making them less chemically etchable.…”

Section: Introductionmentioning

confidence: 99%

Gate etch process model for static random access memory bit cell and FinFET construction

Stout¹,

Rauf²,

Peters³

et al. 2006

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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A reactor/feature/lithography modeling suite has been developed to study the gate etch process. The gate etch process study consists of an eight step process designed to etch through a hard mask (HM)/antireflective coating/polysilicon gate stack and a 22+ step modeled process for FinFET (field effect transistor) manufacture. Coupling to a lithography model allows for a study of how a static random access memory (SRAM) bit cell layout transfers into the gate stack during the gate etch process. The lithography model calculates a three-dimensional (3D) photoresist (PR) profile using the photomask, illumination conditions, and a PR development model. The 3D PR profile is fed into the feature model, Papaya, as the initial PR etch mask condition. The study of the cumulative effect of the gate etch process required to transfer a photomask layout into a gate stack allows for a better understanding of the impact one step in the gate etch process can have on subsequent steps in the process. Studies of pattern transfer of a SRAM bit cell into a gate stack have shown that more edge movement occurs at line ends than at line sides. The line ends are more exposed to incoming etchants and have less opportunity for passivant buildup from the etching wafer than along line sides. An increase in sidewall slope at line ends during the trim and HM etch is observed experimentally and predicted by the model. The slope at line ends during trim and HM etch is more prevalent for narrow ends versus the wider “contact” ends. The lower the PR etch mask height after the HM etch step, the larger the angle seen at line ends which increases the line end pullback. So, a correlation exists between higher wafer power during the HM etch and line end pullback. Passivant formation at the polysilicon sidewall during the main etch/soft landing/overetch polysilicon etch sequence can straighten the profile as well as cause hourglassing and trapezoidal profiles. Passivant thickness, passivant deposition rate, as well as the passivant to polysilicon etch ratio all control this profile behavior. Increased passivation levels also have the tendency to increase linewidth roughness. In FinFET manufacture the gate etch needs to account for the increased topography introduced by the fins.

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Chemical topography analyses of silicon gates etched in HBr/Cl2/O2 and HBr/Cl2/O2/CF4 high density plasmas

Cited by 26 publications

References 13 publications

Correlation and Interaction between Sidewall Passivation and Chamber Walls Deposition During Silicon Gate Etching

Correlation and Interaction between Sidewall Passivation and Chamber Walls Deposition During Silicon Gate Etching

Development of plasma etching processes to pattern sub-15 nm features with PS-b-PMMA block copolymer masks: Application to advanced CMOS technology

Gate etch process model for static random access memory bit cell and FinFET construction

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