Chip Architecture Design Management Based on Low-Power Multitasking Simulation

Abstract

From the aspects of low-power DSP design, low-power SOC design, and low-power power switch design, this paper proposes a chip architecture “high-low matching” scheme for low-power multitasking requirements. The low-power DSP design starts with operating voltage and operating frequency control, and uses three low-power modes, PD1, PD2, and PD3; the low-power SOC design carries out low-power mode management from the clock control of APB and AHB bus; In terms of low-power power switch design, no-load low-power control, and input under-voltage protection, output over-voltage protection, over-temperature protection, and output over-current protection are implemented. The paper proposes different low-power control modes. After the evaluation of the built test platform, it is proved that the design of the scheme is reasonable, and it can realize the engineering application of low-power multi-task management.