Chip Layout Optimization Using Critical Path Weighting

Dunlop, A.E.; Agrawal, Vishwani D.; Deutsch, D.N.; Jukl, M. F.; Kozak, P.; Wiesel, M.

doi:10.1109/dac.1984.1585786

Cited by 96 publications

(15 citation statements)

References 4 publications

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“…Net-based algorithms [Dunlop et al 1984;Nair et al 1989;Tsay and Koehl 1991;Eisenmann and Johannes 1998], on the contrary, do not directly enforce path-based constraints. Instead, timing constraints or requirements on paths are transformed into either net-length constraints or net weights.…”

Section: Net-based Algorithmsmentioning

confidence: 99%

Large-scale circuit placement

Cong¹,

Shinnerl²,

Xie³

et al. 2005

ACM Trans. Des. Autom. Electron. Syst.

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Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and system performance in deep submicron technologies. The placement problem has been studied extensively in the past 30 years. However, recent studies show that existing placement solutions are surprisingly far from optimal. The first part of this tutorial summarizes results from recent optimality and scalability studies of existing placement tools. These studies show that the results of leading placement tools from both industry and academia may be up to 50% to 150% away from optimal in total wirelength. If such a gap can be closed, the corresponding performance improvement will be equivalent to several technology-generation advancements. The second part of the tutorial highlights the recent progress on large-scale circuit placement, including techniques for wirelength minimization, routability optimization, and performance optimization.

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Section: Net-based Algorithmsmentioning

confidence: 99%

Large-scale circuit placement

Cong¹,

Shinnerl²,

Xie³

et al. 2005

ACM Trans. Des. Autom. Electron. Syst.

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“…where R net is computed using the length of the minimum bounding box as in equation (1) and C l 's are calculated from equation (3) in which each l i is calculated from equation (2). By introducing new notation, the propagation delay derived in equation (7) can be simply written as:…”

Section: Delay Formulation IImentioning

confidence: 99%

“…In the net-based approach, after assigning weights to nets and updating these weights based on their timing criticality, the placement algorithm seeks to minimize the total weighted net length by placing the cells in an iterative manner [2] [3] [4] [5] [6] [7]. In the path-based approach, the placement algorithm chooses a fixed number of critical paths after performing timing analysis on the circuit netlist and then seeks to minimize the delay of these paths by placing the cells [8] [9] [10] [11] [12] [13].…”

Section: Introductionmentioning

confidence: 99%

Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points

Ajami

Pedram

2001

Proceedings of the 2001 Conference on Asia South Pacific Design Automation - ASP-DAC '01

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-This paper presents a new algorithm for timingdriven cell placement using the notion of movable IntroductionThe strong demand for complex high performance digital circuits motivates a continuous reduction of the minimum feature size in VLSI process technologies, which in turn introduces new challenges. Specifically, the interconnect delay has become a dominant factor in delay calculations. On the other hand, the strong demand for faster clock speeds calls for more aggressive timingdriven EDA tools. Inconsistency of the delay models that are used in different stages of the EDA flow causes the timing-closure problem (also known as the solution oscillation problem) in conventional flows. In contrast, unification-based approaches, which combine different stages of optimization flow into one integrated step, solve the timing closure problem by using unified timing and data models. To-date, the unification-based approaches have mostly focused on the timing-closure problem between the front-end (synthesis) and back-end (layout) of EDA flows [1].This paper presents a unification-based approach to improve the timing-closure inside the back-end of an EDA flow, which is caused by the inconsistency between the delay calculations performed during the placement and routing stages. In the past, this inconsistency was ignored. However as the interconnect delays become more dominant compared to the gate delays, this conflict cannot be ignored anymore. Timing-driven placement has been studied extensively in the literature. Existing techniques may be classified into two major categories: net-based and path-based.*This work was supported in part by the SRC under contract number 98-DJ-606.In the net-based approach, after assigning weights to nets and updating these weights based on their timing criticality, the placement algorithm seeks to minimize the total weighted net length by placing the cells in an iterative manner By performing global routing after the placement step, the exact topology of each net is determined due to the construction of its Steiner routing tree. There are a number of different Steiner routers based on the objective function used. Earlier works tried to minimize the cost (i.e. the total edge length) of the resulting Steiner routing tree [15]. More recent works attempt to simultaneously minimize the cost and the radius (the longest source-sink path length). In timing-driven global routing (which is our concern in this paper), the objective is to keep the critical-sink (CS) arrival time delay to a minimum while making the routing cost of the net as low as possible [16].Standard backend flow performs timing-driven placement followed by timing-driven global routing. In this flow, the net length model used during placement is based on the bounding-box model or clique model whereas during global routing it is based on the CS-Steiner routing trees. Due to this inconsistency in determining the net lengths, after performing the global routing the delay information of critical paths may significantly change....

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“…To avoid the intersection, nodes n 2 and n 1 will be moved as a group if node n 2 is selected. Hence, the cost to move n 2 is the cost of moving n 2 and n 1 .…”

Section: Algorithmmentioning

confidence: 99%

A construction of minimal delay Steiner tree using two-pole delay model

Lin

Liu

Hwang

2001

Proceedings of the 2001 Conference on Asia South Pacific Design Automation - ASP-DAC '01

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Abstract| In this paper, we will study the construction of a Steiner routing tree for a given net with the objective of minimizing the delay of the routing tree. Previous researches adopt Elmore delay m o d e l to compute delay. However, with the advancement of IC technology, a more accurate delay model is required. Therefore, in this paper, we will use two-pole delay model to compute the cost function of a Steiner tree. Moreover, we propose a new algorithm to construct the Steiner tree. Our algorithm takes into consideration the net topology, the total wire length and the longest path from the source to sink. Experimental results show that our algorithm is very e ective and e cient as compared to 8].

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Chip Layout Optimization Using Critical Path Weighting

Cited by 96 publications

References 4 publications

Large-scale circuit placement

Large-scale circuit placement

Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points

A construction of minimal delay Steiner tree using two-pole delay model

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