Chip Multiprocessor Design Space Exploration through Statistical Simulation

Abstract

Abstract-Developing fast chip multiprocessor simulation techniques is a challenging problem. Solving this problem is especially valuable for design space exploration purposes during the early stages of the design cycle where a large number of design points need to be evaluated quickly. This paper studies statistical simulation as a fast simulation technique for chip multiprocessor (CMP) design space exploration. The idea of statistical simulation is to measure a number of program execution characteristics from a real program execution through profiling, to generate a synthetic trace from it, and simulate that synthetic trace as a proxy for the original program. The important benefit is that the synthetic trace is much shorter compared to a real program trace, which leads to substantial simulation speedups. This paper enhances state-of-the-art statistical simulation: 1) by modeling the memory address stream behavior in a more microarchitecture-independent way and 2) by modeling a program's time-varying execution behavior. These two enhancements enable accurately modeling resource conflicts in shared resources as observed in the memory hierarchy of contemporary chip multiprocessors when multiple programs are coexecuting on the CMP. Our experimental evaluation using the SPEC CPU benchmarks demonstrates average prediction error of 7.3 percent across a range of CMP configurations while varying the number of cores and memory hierarchy configurations.

Analytical Design Space Exploration Based on Statistically Refined Runtime and Logic Estimation for Software Defined Radios

“…design phases and origins of metric variations or number of metrics. For example, [7] explores the origin of runtime variations based on specific microarchitectural parameters, such as cache effects, branching and pipelining, where in our model, any variations can be caputured, including variations from different degree of manual optimization effort during implementation, which is especially important in early design space exploration.…”

“…In [7] task runtime variations are captured in a statistical distribution, which is used as synthetic trace to simulate runtime dynamics. Kempf et al present an analytical framework [12], which uses probability density functions to capture inaccuracies in runtime estimations.…”

High-level simulation of concurrency operations in microthreaded many-core architectures

“…However, these type of simulators are rarely used in generalpurpose multi-or many-core systems. Eeckhout et al have worked on statistical simulation of single-core general-purpose processors [7], [6], [9] and multi-core processors [10]. Similarly, Nussbaum and Smith [23] has also worked on statistical approaches to provide high-level simulation of multi-core processors.…”

ArchRanker: A ranking approach to design space exploration

“…Eeckhout et al proposed an improved statistical simulation framework employing a statistical flow graph to accurately characterize the control flow behavior of a program [9]. To reduce simulation overhead for CMP design, Genbrugge and Eeckhout proposed several statistical quantities to capture the behavior of cache access and shared resource contentions that are critical to the performance of multi-programmed programs running on CMPs [13,14]. Hughes and Li proposed to leverage statistical characteristics that capture the behaviors of memory sharing and inter-thread synchronization when constructing synthetic multi-threaded programs [16].…”