Chip–Package Interaction and Reliability Improvement by Structure Optimization for Ultralow-$k$ Interconnects in Flip-Chip Packages

Abstract

Mechanical failures in low-k interlayer dielectrics and related interfaces during flip-chip-packaging processes have raised serious reliability concerns. The problem can be traced to interfacial fracture induced by chip-package interaction (CPI). During the packaging processes, thermal stresses arise from the mismatch in coefficient of thermal expansion between the chip and the substrate, which can be directly coupled into the Cu/low-k interconnect structure to drive interfacial delamination. In this paper, finite-element method is used to evaluate the crack driving force induced by CPI and to examine its impact on the reliability of Cu/low-k interconnects for 45-nm technology and beyond. First, the characteristics of CPI are investigated for flip-chip packages using a 3-D multilevel global-to-local modeling method where the crack driving force for the interfacial delamination in Cu/low-k interconnect structures is evaluated. The effects of dielectric and packaging materials are examined for different low-k dielectrics and Pb-based and Pb-free solders. This study is then extended to explore the potential of using structural optimizations to improve the CPI reliability as the technology continues with dimensional scaling and implementation of porous ultralow-k materials.Index Terms-Chip-package interaction (CPI), crack stop, Cu/low-k interconnect reliability, finite-element method, low-k dielectric.

The strength of BEOL structures fabricated using low K materials and its impact on CPI failures

“…Calculations made using our multiscale model show that as the thickness of theses layers is increased the strain energy released by a crack in the ULK levels decreases. An example of such a calculation is shown in figure (4) in which reducing the thickness of the oxide levels in a BEOL stack by a factor of two increases the G experienced by a 1 m crack by 40%. Increasing the oxide level thickness by 50% decreases G by 18%.…”

Study on the Manufacturability of XDFOI Package with Organic RDLs (XDFOI-O)

“…Compared to traditional MCM packaging, RDL interposer packaging technology can reduce the distance between chips, significantly reducing the signal connection width and spacing. In addition, compared to Si Integrator, 2.5D RDL interposer eliminates the silicon through via (TSV) process, has lower thermal resistance and better mechanical properties [4][5], and has significant cost advantages. Therefore, 2.5D RDL interposer (named XDFOI-O, X dimension fan out integration [6] with organic RDLs, in this paper) is a more balanced chip solution in all aspects.…”

<em>In Situ</em> Time-dependent Dielectric Breakdown in the Transmission Electron Microscope: A Possibility to Understand the Failure Mechanism in Microelectronic Devices

“…However, this benefit was encroached by the continuing aggressive scaling of microelectronic devices in recent years. The use of low-k/ULK materials results in various challenges in the manufacturing process and for the product reliability, particularly if the interconnect pitch reaches about 100 nm or less [4][5][6] . TDDB refers to the physical failure mechanism of a dielectric material as a function of time under an electric field.…”

“…Shift the energy to the copper M-edge adsorption peak in the EELS. 4. Go back to the imaging mode to acquire an energy filtered TEM image at the Cu M-edge absorption peak.…”