Chip to Wafer Hybrid Bonding with Cu Interconnect: High Volume Manufacturing Process Compatibility Study

Gao, Guanghai; Mrozek, P.; Workman, Thomas; Mirkarimi, Laura; Fountain, G. G.; Theil, Jeremy A.; Guevara, Gabe; Uzoh, Cyprian; Lee, Bongsub; Liu, Ping

doi:10.23919/iwlpc.2019.8913877

Cited by 25 publications

(11 citation statements)

References 6 publications

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“…We propose the use of 1 large strides, 2 large kernel sizes, 3 reduced number of channels, 4 P 2 M custom convolution, and 5 shifted ReLU operation to incorporate the shift term of the batch normalization layer, for emulating accurate P 2 M circuit behaviour. dielectric-to-dielectric direct bonding hybrid process can achieve high-throughput sub-micron pitch scaling with precise vertical alignment 22 . One of the advantages of adapting this heterogeneous integration technology is that chips of different sizes can be fabricated at distinct foundry sources, technology nodes, and functions and then integrated together.…”

Section: Cis Process Integration and Area Considerationsmentioning

confidence: 99%

P2M: A Processing-in-Pixel-in-Memory Paradigm for Resource-Constrained TinyML Applications

Datta¹,

Kundu²,

Yin³

et al. 2022

Preprint

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The demand to process vast amounts of data generated from state-of-the-art high resolution cameras has motivated novel energy-efficient on-device AI solutions. Visual data in such cameras are usually captured in analog voltages by a sensor pixel array, and then converted to the digital domain for subsequent AI processing using analog-to-digital converters (ADC). Recent research has tried to take advantage of massively parallel low-power analog/digital computing in the form of nearand in-sensor processing, in which the AI computation is performed partly in the periphery of the pixel array and partly in a separate on-board CPU/accelerator. Unfortunately, high-resolution input images still need to be streamed between the camera and the AI processing unit, frame by frame, causing energy, bandwidth, and security bottlenecks. To mitigate this problem, we propose a novel Processing-in-Pixel-in-memory (P 2 M) paradigm, that customizes the pixel array by adding support for analog multi-channel, multi-bit convolution, batch normalization, and ReLU (Rectified Linear Units). Our solution includes a holistic algorithm-circuit co-design approach and the resulting P 2 M paradigm can be used as a drop-in replacement for embedding memory-intensive first few layers of convolutional neural network (CNN) models within foundry-manufacturable CMOS image sensor platforms. Our experimental results indicate that P 2 M reduces data transfer bandwidth from sensors and analog to digital conversions by ∼21×, and the energy-delay product (EDP) incurred in processing a MobileNetV2 model on a TinyML use case for visual wake words dataset (VWW) by up to ∼11× compared to standard near-processing or in-sensor implementations, without any significant drop in test accuracy.

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Section: Cis Process Integration and Area Considerationsmentioning

confidence: 99%

P2M: A Processing-in-Pixel-in-Memory Paradigm for Resource-Constrained TinyML Applications

Datta¹,

Kundu²,

Yin³

et al. 2022

Preprint

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“…A convolutional stride of 6 with no pooling leads to a BR of 13.5×, also with a maximum of 64 weight transistors per pixel 2 . Note, using chip stacking in which weight transistors are integrated vertically on a stacked chip through metal-to-metal fusion bonding [10] or through-silicon-vias (TSVs) [21], minimal to no increase in pixel area is expected because of the dense metal-pitch (MP) and contacted poly-pitch (CPP) [11] of advanced technology nodes and the relatively large sizes of underlying pixel arrays.…”

Section: B Bandwidth Vs Number Of Transistorsmentioning

confidence: 99%

P2M-DeTrack: Processing-in-Pixel-in-Memory for Energy-efficient and Real-Time Multi-Object Detection and Tracking

Datta¹,

Kundu²,

Yin³

et al. 2022

Preprint

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Today's high resolution, high frame rate cameras in autonomous vehicles generate a large volume of data that needs to be transferred and processed by a downstream processor or machine learning (ML) accelerator to enable intelligent computing tasks, such as multi-object detection and tracking. The massive amount of data transfer incurs significant energy, latency, and bandwidth bottlenecks, which hinders real-time processing.To mitigate this problem, we propose an algorithm-hardware codesign framework called Processing-in-Pixel-in-Memory-based object Detection and Tracking (P 2 M-DeTrack). P 2 M-DeTrack is based on a custom faster R-CNN-based model that is distributed partly inside the pixel array (front-end) and partly in a separate FPGA/ASIC (back-end). The proposed front-end in-pixel processing down-samples the input feature maps significantly with judiciously optimized strided convolution and pooling. Compared to a conventional baseline design that transfers frames of RGB pixels to the back-end, the resulting P 2 M-DeTrack designs reduce the data bandwidth between sensor and back-end by up to 24×. The designs also reduce the sensor and total energy (obtained from in-house circuit simulations at Globalfoundries 22nm technology node) per frame by 5.7× and 1.14×, respectively. Lastly, they reduce the sensing and total frame latency by an estimated 1.7× and 3×, respectively. We evaluate our approach on the multi-object object detection (tracking) task of the large-scale BDD100K dataset and observe only a 0.5% reduction in the mean average precision (0.8% reduction in the identification F1 score) compared to the state-of-the-art.

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“…The Bi-CIS image sensor chip/die is heterogeneously integrated through a bonding process (die-to-die or die-to-wafer) integrating it onto the die consisting of weight transistors. Preferably, a die-to-wafer low-temperature metal-to-metal fusion with a dielectric-to-dielectric direct bonding hybrid process can achieve high-throughput sub-micron pitch scaling with precise vertical alignment 23 . One of the advantages of adapting this heterogeneous integration technology is that chips of different sizes can be fabricated at distinct foundry sources, technology nodes, and functions and then integrated together.…”

Section: Re-purposing Digital Correlated Double Sampling Circuit and ...mentioning

confidence: 99%

A processing-in-pixel-in-memory paradigm for resource-constrained TinyML applications

Datta

Kundu

Yin

et al. 2022

Sci Rep

View full text Add to dashboard Cite

The demand to process vast amounts of data generated from state-of-the-art high resolution cameras has motivated novel energy-efficient on-device AI solutions. Visual data in such cameras are usually captured in analog voltages by a sensor pixel array, and then converted to the digital domain for subsequent AI processing using analog-to-digital converters (ADC). Recent research has tried to take advantage of massively parallel low-power analog/digital computing in the form of near- and in-sensor processing, in which the AI computation is performed partly in the periphery of the pixel array and partly in a separate on-board CPU/accelerator. Unfortunately, high-resolution input images still need to be streamed between the camera and the AI processing unit, frame by frame, causing energy, bandwidth, and security bottlenecks. To mitigate this problem, we propose a novel Processing-in-Pixel-in-memory (P2M) paradigm, that customizes the pixel array by adding support for analog multi-channel, multi-bit convolution, batch normalization, and Rectified Linear Units (ReLU). Our solution includes a holistic algorithm-circuit co-design approach and the resulting P2M paradigm can be used as a drop-in replacement for embedding memory-intensive first few layers of convolutional neural network (CNN) models within foundry-manufacturable CMOS image sensor platforms. Our experimental results indicate that P2M reduces data transfer bandwidth from sensors and analog to digital conversions by $${\sim }\,21\times$$ ∼ 21 × , and the energy-delay product (EDP) incurred in processing a MobileNetV2 model on a TinyML use case for visual wake words dataset (VWW) by up to $$\mathord {\sim }\,11\times$$ ∼ 11 × compared to standard near-processing or in-sensor implementations, without any significant drop in test accuracy.

show abstract

Chip to Wafer Hybrid Bonding with Cu Interconnect: High Volume Manufacturing Process Compatibility Study

Cited by 25 publications

References 6 publications

P2M: A Processing-in-Pixel-in-Memory Paradigm for Resource-Constrained TinyML Applications

P2M: A Processing-in-Pixel-in-Memory Paradigm for Resource-Constrained TinyML Applications

P2M-DeTrack: Processing-in-Pixel-in-Memory for Energy-efficient and Real-Time Multi-Object Detection and Tracking

A processing-in-pixel-in-memory paradigm for resource-constrained TinyML applications

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