Chisel Usecase: Designing General Matrix Multiply for FPGA

Abstract

To ease developers work in an industry where FPGA usage is constantly growing, we propose an alternative methodology for architecture design. Targetting FPGA boards, we aim at comparing implementations on multiple criteria. We implement it as a tool flow based on Chisel, taking advantage of high level functionalities to ease circuit design, evolution and reutilization, improving designers productivity. We target a Xilinx VC709 board and propose a case study on General Matrix Multiply implementation using this flow, which demonstrates its usability with performances comparable to the state of the art, as well as the genericity one can benefit from when designing an applicationspecific accelerator. We show that we were able to generate, simulate and synthesize 80 different architectures in less than 24 hours, allowing differents trade-offs to be quickly and easily studied, from the most performant to the less costly, to easily comply with integration constraints.

Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration

“…This is mainly due to a reduction of synthesis timeouts, as synthesis runs which does not converge in the exhaustive strategy are estimated at RTL level as consuming too many resources, and are not even considered as candidates for synthesis in the gradient based strategy. Achieved optimal implementation reaches a theoretical performance of 231.334 GOp/s on target board, which is coherent with the original solution [22] -and is comparable to state of the art solutions -showing that process did not alter design performances.…”

“…We chose to implement a generic estimation technique with principle similar to Schumacher et al [17] and integrate it in standard Chisel flow as a proof-of-concept. We then used a Chisel based GEMM circuit generator to demonstrate our novel exploration methodology, based on previous work from Ferres et al [22].…”

“…As a way to demonstrate the usage of such estimators for DSE processes, we chose to explore a General Matrix Multiply (GEMM) circuit generator already introduced in previous work [22]. This GEMM generator aims at maximizing I/O throughput by consuming input data only once, and we hence aim at exploring implementations on such criterion.…”

“…For this exploration process, we chose to maximize design theoretical throughput (in GOp/s), using a simple analytical formula to derive it from both generation parameters and operating frequency as given by the result of synthesis processes. As Ferres et al [22] showed that experimental latency obtained in simulation only differed from theoretical latency by few cycles, which is negligible with respect to the order of magnitude of the problem, we use theoretical throughput as a performance metric for such exploration. Based on the same work, we used the maximum percentage of resource usage for the 4 resource considered -LUTs, Flip Flops, DSPs and BRAMs -as cost metric, as saturating one resource will result in non placeable designs.…”