CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out

Abstract

Spin-torque transfer magnetic random access memory (STT-MRAM) based computation-in-memory (CIM) architectures have shown great prospects for energy-efficient computing. However, device variations and non-idealities narrow down the sensing margin that severely impacts the computing accuracy. In this work, we propose an adaptive referencing mechanism to improve the sensing margin of a CIM architecture for boolean binary logic (BBL) operations. We generate reference signals using multiple STT-MRAM devices and place them strategically into the array such that these signals can address the variations and trace the wire parasitics effectively. We have demonstrated this behavior using STT-MRAM model, which is calibrated using 1Mbit characterization array. Results show that our proposed architecture for binary neural network (BNN) achieves up to 17.8 TOPS/W on the MNIST dataset and 130× performance improvement for text encryption compared to the software implementation on CPU.

Dependability of Future Edge-AI Processors: Pandora’s Box

“…Solutions for mitigating the impact of non-idealities can be developed at various abstraction levels such as circuit-level [28], architecture-level [29] and application-level [5]. Next two solution examples will be illustrated.…”

Demeter: A Fast and Energy-Efficient Food Profiler Using Hyperdimensional Computing in Memory

“…Resistive memories or memristive devices, such as ReRAM, PCM, and STT-MRAM [59,69,119,132], have recently been introduced as suitable candidates for both storage and computation units that can efficiently perform vector-matrix multiplication [138] and logical bulk bit-wise operations [26,73,113,114,139], as they can follow Kirchhoff's law inherently [121]. Therefore, many recent works [9,26,27,111,112,139,[143][144][145] exploit these devices in their CIM architectures.…”

“…Therefore, many recent works [9,26,27,111,112,139,[143][144][145] exploit these devices in their CIM architectures. Memristor devices also enjoy non-volatility, highdensity, and near-zero standby power [73,119,139].…”

“…Many previous works investigate how to provide new functionality using compute-capable memories based on conventional (e.g., [1,2,36,40,43,72,99,108,110]) and emerging memory technologies (e.g., [9,27,56,59,68,73,101,111,116,117,119,121,139,144]) to help solve the data movement overheads in today's systems. These works propose new functionality in at least three major categories: (1) support for logical operations (e.g., [26,73,86,110,119,121,139,144]), (2) support for complex operations, functions, and applications (e.g., [1,36,72,89,111,112,116,117,143]), and (3) programming and system support for the integration and adoption of such accelerators (e.g., [2,3,9,19,27,55,…”

“…(2) They use costly Machine Learning (ML) techniques such as skip connections 1 [96,123,140], leading to added computation, memory, and storage overheads (e.g., to store the activation parameters that are fed to the last layers of the NN) [120]. Therefore, over the past decade, both industry and academia [27,68,101,111,115,119] have explored the use of Computation-In-Memory (CIM) 2 using memristor-based devices to accelerate DNNs.…”