Circuit aging prediction for low-power operation

Zheng, Rui; Velamala, Jyothi; Reddy, V.; Balakrishnan, Varsha; Mintarno, Evelyn; Mitra, Subhasish; Krishnan, S.; Cao, Yu

doi:10.1109/cicc.2009.5280814

Cited by 39 publications

(19 citation statements)

References 5 publications

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“…Such behavior has been experimentally observed in [7] and [27]. Improved knowledge of system aging slack can enhance the quality of the control decision made, which in turn improves self-tuning benefits.…”

Section: Evaluates the Power Consumption P (I) And The Delay At The Ementioning

confidence: 85%

“…Based on [7], V IT(i+1) can be expressed as a function of V IT(i) and dynamic operating conditions between time-steps i and (i + 1). During active mode when V dd is turned on, the system experiences dynamic-stress condition where both the stress phase and recovery phase alternately impact aging (Fig.…”

Section: E Threshold Voltagementioning

confidence: 99%

“…4. Calibration of aging model using 45 nm experiment data in [7]. The first figure shows continuous active mode for various V dd and temperature.…”

Section: G Temperaturementioning

confidence: 99%

“…For alternating active/sleep modes, the presence of a long recovery phase during sleep mode significantly changes the diffusion profile that continues into the subsequent active mode. Hence, special aging models and boundary conditions are required to connect the next active mode with the sleep mode-otherwise, degradation can be over-estimated [7].…”

Section: E Threshold Voltagementioning

confidence: 99%

“…Depending on the design and the operating conditions, this may result in more than 20% speed degradation [1]- [4]. Aging-induced changes in the interface charge depend on the process technology and several dynamic factors: the amount of time elapsed, temperature, workload, and voltage profiles [5]- [7]. While we focus on NBTI, it is possible to extend our framework for other reliability mechanisms, e.g., Positive Bias Temperature Instability (PBTI), Electromigration (EM), Time Dependent Dielectric Breakdown (TDDB), Gate Oxide Integrity (GOI), Thermal Cycling (TC), and Hot Carrier Injection (HCI).…”

mentioning

confidence: 99%

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Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Mintarno

Skaf

Zheng

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents an integrated framework, together with control policies, for optimizing dynamic control of self-tuning parameters of a digital system over its lifetime in the presence of circuit aging. A variety of self-tuning parameters such as supply voltage, operating clock frequency, and dynamic cooling are considered, and jointly optimized using efficient algorithms described in this paper. Our optimized self-tuning approach satisfies performance constraints at all times, and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. We present three control policies: 1) progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2) progressive-on-stateaging (POSA), which estimates aging by tracking active/sleep modes, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; and 3) progressive-real-timeaging-assisted (PRTA), which acquires real-time information and initiates optimized control actions. Various flavors of these control policies for systems with dynamic voltage and frequency scaling (DVFS) are also analyzed. Simulation results on benchmark circuits, using aging models validated by 45 nm measurements, demonstrate the effectiveness and practicality of our approach in significantly improving LCPE and/or lifetime compared to traditional one-time worst-case guardbanding. We also derive system design guidelines to maximize self-tuning benefits.Index Terms-Adaptive supply voltage and clock frequency, circuit aging, energy-efficiency, lifetime reliability.

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Section: Evaluates the Power Consumption P (I) And The Delay At The Ementioning

confidence: 85%

Section: E Threshold Voltagementioning

confidence: 99%

“…4. Calibration of aging model using 45 nm experiment data in [7]. The first figure shows continuous active mode for various V dd and temperature.…”

Section: G Temperaturementioning

confidence: 99%

Section: E Threshold Voltagementioning

confidence: 99%

mentioning

confidence: 99%