Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching

Abstract

The main aim of this work is to study the effect of symmetric and asymmetric spacer length variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire (NW) FET at 10 nm gate length (L G ). Spacer length is proved to be one of the stringent metrics in deciding device performance along with width, height and aspect ratio (AR). The physical variants in this work are symmetric spacer length (L SD ), source side spacer length (L S ) and drain side spacer length (L D ). The simulation results give highest I ON /I OFF ratio with L D variation compared to L S and L SD , whereas latter two variations have similar effect on I ON /I OFF ratio. At 25 nm (2.5 × L G ) of L D , the device gives appreciable ON current with the highest I ON /I OFF ratio (2.19 × 10 8 ) with optimum subthreshold slope (SS) and ensures low power and high switching drivability. Moreover, it is noticed that among optimal values of L S and L D , the device I ON /I OFF ratio has an improvement of 22.69% as compared to other variations. Moreover, the effect of various spacer dielectrics on optimized device is also investigated. Finally, the CMOS inverter circuit analysis is performed on the optimized symmetric and asymmetric spacer lengths.

Design and optimization of vertical nanowire tunnel FET with electrostatic doping

“…However, the I ON can still be modified to a higher level by using the gate stacking technique and this device can be used for low power circuit implementation. 8.2×10 9 70.37 39.5 GC-IG-NWTFET [36] 4.2×10 8 74 8 DMG-HD-VTFET [37] 2.6×10 11 18.1 -GAA Nanowire FET [38] 3.19×10 8 61.5 -Multi Bridge channel FET [39] 1.7×10…”

“…Here IIP3 & VIP3 of the proposed device are higher, and IMD3 is lower than the other devices [30][31][32] with the lower value of VIP2. Thus the proposed device Inner-Gated NWTFET [36], Dual Material Gate Heterogeneous Dielectric Vertical TFET [37], GAA Nanowire FET [38], Multi Bridge channel FET [39] and Nanosheet FET [40] are compared with proposed device Electrostatically doped Vertical Nanowire TFET & it is observed that E-VNWTFET is having better I ON /I OFF, Lower DIBL and better subthreshold slope than most of the devices.…”

Common Source Amplifier and Ring Oscillator Circuit Performance Optimization Using Multi-Bridge Channel FETs

“…The gain bandwidth product (GBW) is used to estimate the device efficacy in high frequency applications. 23 Mathematically GBW can be evaluated as: 26 GBW g C 20 6…”

Impact of Scaling on Nanosheet FET and CMOS Circuit Applications

“…9,10 Researchers came up with the implementation of high-k gate stack to combat this problem. 11 Also, multiple device engineering such as Silicon on Insulator (SOI) technology, 12 2D channel materials, 13 Double gate (DG), 14 Trigate, 15 Fin-shaped field effect transistor (FinFET), 16 gate all around (GAA) FETs [17][18][19][20] are implemented. In the DG transistor, the gate is present at the top and down sides of the channel and improves the gate's electrostatic integrity and offers better short channel performance.…”