Circuit design challenges at the 14nm technology node

Abstract

Technology scaling non-idealities, already apparent in the transitions between previous technology generations, will become even more pronounced as the world moves from the 22nm node to the 14nm node. Digital logic designers working on highperformance microprocessors and similar projects will face significant new challenges as the basic FET structure is changed in a fundamental way, in order to squeeze more performance from scaled devices. New design constraints and new sources of variability will have to be understood, and new methodologies will be required to enable robust, high-speed designs. In addition, the metal interconnects between devices will also be stressed. Scaled wire RC will likely increase, and new tools and methods will be needed to ensure reliable designs.

Architecting NP-Dynamic Skybridge

“…Large resistance and capacitance from interconnections cause significant degradation in circuit's performance and power. Microprocessor's performance is faced with a corner and taken into a bottleneck [4]. And the power density of a microprocessor will soon climb beyond the capabilities of any possible cooling techniques in the future.…”

Redundancy-aware Electromigration checking for mesh power grids

“…Specifically, electromigration (EM) has re-emerged as a significant problem in modern chip design and there are three problems that demand attention: 1) existing EM checking techniques for the power grid are overly pessimistic (because of an underlying series system assumption, as will be explained later), leading to loss of safety margins and multiple design iterations, 2) increased current density in grid metal lines has led to a significant loss of margins between the predicted EM stress and the allowed thresholds, and 3) checking modern, large power grids for EM has become very expensive. To make things worse, it is forecast [1] [2] that metal line current density and reliability due to EM will get dramatically worse with continued technology scaling. As a result, EM signoff has become increasingly difficult and designers are forced to reconsider traditional approaches, and to look with suspicion at the large safety margins and pessimism built into traditional EM checking methods.…”

Impact of range and precision in technology on cell-based design

“…FinFETs and other multi-gate devices are considered to be an alternative for conventional CMOS devices as they offer improved leakage power, reduced parasitic capacitances, and improved resistance to parametric variability [12,8]. These devices feature fully-depleted channels, and have gates that surround the channel on three sides, offering superior control of the channel.…”

“…The v th can be adjusted by changing the gate workfunction [12], or by using the device as a three terminal device [7]. Researchers at the commercial foundry state that multi-v th options can be provided by the FinFET family [13], however the limited availability of v th options to a designer will limit the design space very significantly, as in Figure 11(a).…”

“…as 1x, 2x, 3x, 4x, etc [8]. In addition, having a wide array of threshold voltages may not be possible [12], and thus, to understand the impact of these restrictions on the power and delay tradeoffs, we examine the impact of the range and precision on standard cell-based designs.…”