Circuit design of a novel adaptable and reliable L1 data cache

Abstract

This paper proposes a novel adaptable and reliable L1 data cache design (Adapcache) with the unique capability of automatically adapting itself for different supply voltage levels and providing the highest capacity. Depending on the supply voltage level, Adapcache defines three operating modes: In high supply voltages, Adapcache provides reliability through single-bit parity. In middle range of supply voltages, Adapcache writes data to two separate cache-lines simultaneously in order to use one line for error recovery when the other line is faulty. In near threshold supply voltages, Adapcache writes data to three separate cachelines simultaneously in order to provide the correct data based on bitwise majority voter.

VESPA: VIPT Enhancements for Superpage Accesses

“…We performed a comprehensive study of how cache access latency and lookup energy vary as a function of associativity across several cache sizes using Cacti 6.5 [15], at a 32nm node 3 . L1 caches are tightly coupled to the CPU pipeline, and need to be optimized for both latency and energy.…”

“…On one hand, this allows architects to grow TLBs bigger. On the other hand, VIPT presents challenges in balancing 1 - 3 . The key problem is this -in VIPT designs, the bits used to select the cache set must reside entirely within the page offset of the requested virtual address, as shown in Figure 1.…”

“…Superpages have historically been used to reduce TLB misses. In this work, we go beyond, and leverage the prevalence of superpages to realize VIPT caches that can achieve 1 , 2 , and 3 .…”

“…Consequently, VESPA improves performance ( 1 ) and energy efficiency ( 2 ). Moreover, it leverages the current TLB-L1 interface, and only modestly changes the L1 microarchitecture, making it easy to implement ( 3 ). In other words, VESPA improves, but still conceptually uses the concept of VIPT, and satisfies three types of lookups: a CPU lookups for data in a superpage: VESPA checks fewer L1 cache ways than traditional VIPT caches, reducing hit time and saving energy.…”

On the characterization and optimization of system-level vulnerability for instruction caches in embedded processors

“…Incorrect data values/instructions once read out from the data/instruction caches may crash the subsequent computation/communication, external memory, or storage systems, leading to overall system failures or program inaccuracy. As a critical requirement for reliable computing [5], protecting the information integrity in cache memories has captured a wealth of research efforts [5][6] [7][8] [9][10] [11] [12][13] [14][15] [16].…”