2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015] 2015
DOI: 10.1109/iccpct.2015.7159452
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Circuit level technique for mitigating effects of NBTI for wide fan-in domino logic circuits using supply voltage tuning

Abstract: Transistor ageing has been a major problem as far as nanometre technology is concerned which leads to performance degradation and reliability issues. Ageing in pMOS transistor takes place due to Negative bias temperature instability (NBTI) which is a major threat in reliability as Iscale down the transistor geometries aggressively in our quest for low power and high performance. Overcoming ageing effect requires additional power expense, which in turn aggravates the power and heating problem. I propose an adap… Show more

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Cited by 3 publications
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“…In [38], a negative capacitance was adopted in conjunction with the node with the highest parasitic capacitance, thus improving the timing yield. S. Narang has proposed varying the supply voltage in order to compensate for the negative bias temperature instability [39]. P. K. Pal et al have proposed using a voltage comparison circuit in order to achieve a smaller power dissipation and higher speed by reducing the current of stacked transistors and the number of switching nodes [40].…”
mentioning
confidence: 99%
“…In [38], a negative capacitance was adopted in conjunction with the node with the highest parasitic capacitance, thus improving the timing yield. S. Narang has proposed varying the supply voltage in order to compensate for the negative bias temperature instability [39]. P. K. Pal et al have proposed using a voltage comparison circuit in order to achieve a smaller power dissipation and higher speed by reducing the current of stacked transistors and the number of switching nodes [40].…”
mentioning
confidence: 99%