Circuit optimization using device layout motifs

Xiao, Yang; Trefzer, Martin A.; Roy, S.; Walker, James Alfred; Bale, Simon J.; Tyrrell, Andy M.

doi:10.1109/vari.2014.6957081

Cited by 2 publications

(2 citation statements)

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“…In extreme cases, this is simply to allow designs to be functionally and operationally correct. In order to achieve [2] this aim, new materials, devices and circuit topologies are suggested to enhance robust product functionality and performance [1]. Alternatively, improving circuit performance through technology optimisation such as layout optimisation has been an interesting avenue of research [2]- [5].…”

Section: Introductionmentioning

confidence: 99%

“…In order to achieve [2] this aim, new materials, devices and circuit topologies are suggested to enhance robust product functionality and performance [1]. Alternatively, improving circuit performance through technology optimisation such as layout optimisation has been an interesting avenue of research [2]- [5]. Thus, to investigate the device layout effects on circuit performance, device layout motif using irregular layout is proposed (such as O shape device layout motif that is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

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Circuit design optimisation using a modified genetic algorithm and device layout motifs

Xiao

Walker

Bale

et al. 2014

2014 IEEE International Conference on Evolvable Systems

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Circuit performance optimisation such as increasing speed and minimizing power consumption is the most important design goal for circuit designers next to correct functionality. This is generally also a very complex problem where, in order to solve it, several factors such as device characteristics, circuit topology, and circuit functionality must be considered. Particularly, as technology has scaled to the atomistic level, the resulting uncertainty factors further affect circuit performance. In this paper, we propose combining a modified genetic algorithm with dynamic gene mutation and device layout motif selection for circuit performance improvement. We explore novel device layout motifs (O shape device) to exploit effects of device layout at the atomistic level in order to improve characteristics of circuits and combine them with a modified GA for automatic circuit optimisation. Additionally, in order to overcome local optima and premature convergence, a dynamic gene mutation rate is performed within the GA. The experimental results show that this methodology can achieve more than 30% delay reduction through mixed combinations of O shape devices and regular devices in a circuit, compared to circuits built of only regular devices. At the same time, the local optima are also reliably avoided due to the dynamic gene mutation.

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