2020
DOI: 10.7567/1347-4065/ab6569
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Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs

Abstract: This study investigated the device optimization scheme of a double-gate hetero-junction tunnel FET, which was expected to improve circuit performance. A thinner channel with a stronger electric field increases the tunnel on-current. Conversely, a thin channel results in a larger quantum sub-band energy and an effective bandgap, which decreases the tunnel on-current. Such tradeoffs are clarified by considering the quantum effects in a device simulation. Furthermore, the gate capacitance behavior, identified via… Show more

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Cited by 2 publications
(1 citation statement)
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References 29 publications
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“…In general, in the case of complementary circuits, similar characteristics are preferred for NPN and PNP transistors. Thus, for circuit analysis, we assumed that the polarity-reversed characteristics 12) of the PNP-lateral HBTs were NPN HBTs.…”
Section: Introductionmentioning
confidence: 99%
“…In general, in the case of complementary circuits, similar characteristics are preferred for NPN and PNP transistors. Thus, for circuit analysis, we assumed that the polarity-reversed characteristics 12) of the PNP-lateral HBTs were NPN HBTs.…”
Section: Introductionmentioning
confidence: 99%