Circular-contour-based obstacle-aware macro placement

Chiou, Chien-Hsiung; Chang, Chuen Chau; Chen, Szu-To; Chang, Yao‐Wen

doi:10.1109/aspdac.2016.7428007

Cited by 14 publications

(5 citation statements)

References 16 publications

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“…One of the main challenges of such approaches is the modeling of standard cell logic. Some consider cell area implicitly by having macros close to circuit walls, e.g., initially in [5] and also in the recent works based on circular contours [3], [6], [7]. This is de facto the chosen approach for some industrial floorplanning tools.…”

Section: Previous Workmentioning

confidence: 99%

RTL-Aware Dataflow-Driven Macro Placement

Vidal-Obiols

Cortadella

Petit

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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When RTL designers define the hierarchy of a system, they exploit their knowledge about the conceptual abstractions devised during the design and the functional interactions between the logical components. This valuable information is often lost during physical synthesis. This paper proposes a novel multi-level approach for the macro placement problem of complex designs dominated by macro blocks, typically memories. By taking advantage of the hierarchy tree, the netlist is divided into blocks containing macros and standard cells, and their dataflow affinity is inferred considering the latency and flow width of their interaction. The layout is represented using slicing structures and generated with a top-down algorithm capable of handling blocks with both hard and soft components, aimed at wirelength minimization. These techniques have been applied to a set of large industrial circuits and compared against both a commercial floorplanner and handcrafted floorplans by expert back-end engineers. The proposed approach outperforms the commercial tool and produces solutions with similar quality to the best handcrafted floorplans. Therefore, the generated floorplans provide an excellent starting point for the physical design iterations and contribute to reduce turnaround time significantly.

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Section: Previous Workmentioning

confidence: 99%

RTL-Aware Dataflow-Driven Macro Placement

Vidal-Obiols

Cortadella

Petit

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…It was extended by [9] for routability and blockage-awareness. In [11], three major drawbacks to the use of these previous approaches in modern flows (related to overlap avoidance, preplaced macros, and area utilization) were presented and CPtrees were proposed, aiming also to optimize the shape and area of the region for standard cells. However, the approach lacked scalability.…”

Section: Related Workmentioning

confidence: 99%

Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods

Vidal-Obiols

Cortadella

Petit

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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When RTL designers define the hierarchy of a system, they exploit their knowledge about the conceptual abstractions devised during the design and the functional interactions between the logical components. This valuable information is often lost during physical synthesis. This paper proposes HiDaP, a novel multi-level algorithm that uses RTL information and analytical methods for the macro placement problem of modern designs dominated by multi-cycle connection pipelines. By taking advantage of the hierarchy tree, the netlist is divided into blocks containing macros and standard cells, and their dataflow affinity is inferred considering the register latency and flow width of their interaction. The layout is represented using slicing structures and generated with a top-down algorithm capable of handling blocks with both hard and soft components. An adaptive multi-objective cost function is used to simultaneously minimize wirelength, timing, overlap and distance to preferred locations, which can be user-defined or generated by analytic methods (spectral and force-directed). These techniques have been applied to a set of large industrial circuits and compared against state-of-theart commercial and academic placers, and also to handcrafted floorplans generated by expert back-end engineers. The proposed approach outperforms previous algorithmic methods and can produce solutions with better wirelength and timing than the best handcrafted floorplans. Post-routing layouts are almost brought to timing closure and DRC cleanness with minimal engineer modification, showing that the generated floorplans provide an excellent starting point for the physical design flow and contribute to reduce turnaround time significantly.

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“…The shapes of all five designs are squares 1 , whose sizes range from 800 µm to 1500 µm. For each circuit design, at least 300 different floorplans are generated by placing macros at different locations with the "obstacle-aware macro placement" algorithm [5]. Though placed differently, macros all tend to locate near the chip boundary in order to leave plenty of space at chip center region, where routing demand tends to be high.…”

Section: Drc Hotspot Detectionmentioning

confidence: 99%

RouteNet

Xie

Huang

Fang

et al. 2018

Proceedings of the International Conference on Computer-Aided Design

153

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Early routability prediction helps designers and tools perform preventive measures so that design rule violations can be avoided in a proactive manner. However, it is a huge challenge to have a predictor that is both accurate and fast. In this work, we study how to leverage convolutional neural network to address this challenge. The proposed method, called RouteNet, can either evaluate the overall routability of cell placement solutions without global routing or predict the locations of DRC (Design Rule Checking) hotspots. In both cases, large macros in mixed-size designs are taken into consideration. Experiments on benchmark circuits show that RouteNet can forecast overall routability with accuracy similar to that of global router while using substantially less runtime. For DRC hotspot prediction, RouteNet improves accuracy by 50% compared to global routing. It also significantly outperforms other machine learning approaches such as support vector machine and logistic regression.

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Circular-contour-based obstacle-aware macro placement

Cited by 14 publications

References 16 publications

RTL-Aware Dataflow-Driven Macro Placement

RTL-Aware Dataflow-Driven Macro Placement

Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods

RouteNet

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