Clairvoyant: a synthesis system for production-based specification

Seawright, Andrew; Brewer, Forrest

doi:10.1109/92.285744

Cited by 59 publications

(30 citation statements)

References 18 publications

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“…First, we introduce non-determinism as a preferred representation for protocols. The work described in [9] supports this decision. Second, and more importantly, our formulation is hierarchical and amenable to abstraction.…”

Section: Introductionsupporting

confidence: 64%

A model for scheduling protocol-constrained components and environments

Haynal

Brewer

1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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This paper presents a technique for highly constrained event sequence scheduling. System resource protocols as well as an external interface protocol are described by non-deterministic finite automata (NFA). All valid schedules which adhere to interfacing constraints and resource bounds for flow graph described behavior are determined exactly. A model and scheduling results are presented for an extensive design example.

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Section: Introductionsupporting

confidence: 64%

A model for scheduling protocol-constrained components and environments

Haynal

Brewer

1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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“…Figure 3 depicts the synthesis process beginning with construction of abstract syntax trees (AST) for each pyPBS production. The ASTs are subsequently combined to form a single production directed acyclic graph (DAG) [13]. By using binary decision diagrams (BDD) to represent the logic at each node, a circuit can be directly extracted from the production DAG.…”

Section: Pypbsmentioning

confidence: 99%

Extensible control architectures

Hoover

Brewer

Sherwood

2006

Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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Architectural advances of modern systems has often been at odds with control complexity, requiring significant effort in both design and verification. This is particularly true for sequential controllers, where machine complexity can quickly surpass designer ability. Traditional solutions to this problem require elaborate specifications that are difficult to maintain and extend. Further, the logic generated from these specifications bares no resemblance to the intended behavior and often fails to meet design performance constraints. In the process of designing a multi-threaded, dynamically-pipelined microcontroller, we encountered a number of common difficulties that arise from the inadequacies of traditional pipeline design methodologies. Through the use of a novel nondeterministic finite automata (NFA) specification model, we were able to implement an extensible control structure with minimal design effort. In this paper we present a viable pipeline controller specification methodology using the pyPBS language, which enables minimal effort control partitioning and compact behavioral representation. The structure of the language encourages design decisions that promote efficient modular constructions which can be easily integrated and extended. We present an overview of the our methodology including background on the pyPBS synthesis model, an architectural overview of our multi-threaded microcontroller, and implementation details for the control structure of the design including the complete control specifications. In addition, we show that the applicative nature of the pyPBS language allows for addition of a multi-cycle multiplication unit with minimal effort.

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“…It is based on previous work by Seawright and Brewer, and later Crews, on logic synthesis from grammatical productions [Sea94,Cre96]. Protocol Compiler was first described in [Sea96] and an application for SDH/SONET is shown in [Mey97].…”

Section: Related Workmentioning

confidence: 99%

Design of a SPDIF receiver using protocol compiler

Holtmann

Blinzer

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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This paper describes the design of a receiver for the digital audio signal SPDIF used by CD-ROM players. The design was done with Protocol Compiler, a high-level synthesis tool for the design of structured data stream processing controllers. Compared to traditional RTL design, ProtocolCompiler makes entry, debugging, and re-use easier. Design time was cut by factor 2 while the results in terms of area and delay are competitive.

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Clairvoyant: a synthesis system for production-based specification

Cited by 59 publications

References 18 publications

A model for scheduling protocol-constrained components and environments

A model for scheduling protocol-constrained components and environments

Extensible control architectures

Design of a SPDIF receiver using protocol compiler

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