Classification and Elimination of Conflicts in Hardware Transactional Memory Systems

Abstract

This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts. These conflicts can cause performance and energy losses due to aborts and extra communication. To quantify losses, the paper first proposes the 5C cache-miss classification model that extends the well-established 4C model with a new class of cache misses known as contamination misses. The paper also contributes with two techniques for removal of data conflicts: One for removal of false sharing conflicts and another for removal of silent store conflicts. In addition, it revisits and adapts a technique that is able to reduce losses due to both true and false conflicts. All of the proposed techniques can be accommodated in a lazy versioning and lazy conflict resolution HTM built on top of a MESI cache-coherence infrastructure with quite modest extensions. Their ability to reduce performance is quantitatively established, individually as well as in combination. Performance is improved substantially.

SCIN-cache

“…The FASTM cache allows speculatively modified lines to be gang-invalidated on abort, effectively speeding up the rollback phase and avoiding software handler intervention. However, this approach may slow down the re-execution of aborted transactions due to the encounter of additional L1 misses for such contaminated lines [Waliullah and Stenstrom 2011], as the L1 is not able to hold both clean and speculative copies of the data. For the experiments with FASTM, we did not run any SMT configurations, but simply set up the simulation to use 16 single-threaded cores.…”

“…The Base configuration, which essentially applies simple optimizations to the LogTM design to mitigate these overheads (like avoiding trapping to software when the undo log is empty) performs fairly competitively to the three better performing configurations. The SCIN-cache designs perform noticeably better than FASTM in high contention, due to their improved cache performance: By retaining a clean copy of speculatively updated lines in L1 cache, they avoid contamination misses [Waliullah and Stenstrom 2011] when transactions reexecute. This is visible in Table XII, whose first four data columns show the average number of cache misses per transaction for the systems plotted in Figure 9.…”

Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory

“…We refer to such an event as an abort miss. Such misses have also been referred to as contamination misses [18]. Workloads with large write sets and high contention over small amounts of shared data would experience the greatest drop in private cache hit rates.…”

Zebra

“…Keeping such writes away from the cache improves performance by reducing the number of contamination misses [18] -misses due to invalidation of speculatively updated lines on aborts -and redundant permission downgrades from exclusive or dirty state to shared state (which we term downgrade misses) that allow detection of conflicts. Moreover, this also mitigates the effect of false writerwriter conflicts.…”