Classification based scheduling in Heterogeneous ISA Architectures

Boran, Nirmal Kumar; Yadav, Dinesh Kumar; Iyer, Rishabh

doi:10.1109/vdat50263.2020.9190559

Cited by 4 publications

(1 citation statement)

References 15 publications

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“…We were heavily inspired by more recent work on performance modeling of both software [15,16,24,25,30,31,38,52,56,64,65] and hardware [9,10,19,20,27,28,37]. In particular, we borrowed the notion of performance interfaces as programs from PIX [30] and Freud [56], although both use such interfaces for software running on general-purpose hardware and neither can reason about throughput.…”

Section: Related Workmentioning

confidence: 99%

The Case for Performance Interfaces for Hardware Accelerators

Iyer

Argyraki

et al. 2023

Proceedings of the 19th Workshop on Hot Topics in Operating Systems

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While systems designers are increasingly turning to hardware accelerators for performance gains, realizing these gains is painstaking and error-prone. It can take several person-months to determine if a given accelerator is a good fit for a given piece of code, and accelerators that cost millions of dollars to build can slow down the very systems they were designed to accelerate.We argue that hardware accelerators must come with performance interfaces-interfaces that provide usable information about the accelerator's performance behavior just like semantic interfaces do for functionality-to facilitate their correct use. Since accelerators do not provide new functionality and are only useful if they improve system performance, performance interfaces are as integral to their correct use as semantic interfaces.

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