Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks

Electronic Circuits Diagnosis Using Artificial Neural Networks

“…A production rule based concept was reported in (Pipitone et al, 1991). ANNs have previously been applied to diagnosis (Spina & Upadhyaya, 1997;Materka, 1994;Rodrigez et al, 1994;Aminian & Aminian, 2000;He et al, 2002;Andrejević & Litovski, 2004;Aminian et al, 2002;Stopjakova et al, 2004;Yu et al, 1994;Collins et al, 1994;Catelani & Gori, 1996;Maidon et al, 1997;Yang et al, 2000). As in the case with the classical concepts, however, ANNs were predominantly applied to linear analogue circuits.…”

“…The ANN creates the probability that a circuit is faulty and points to the type of fault. In (Stopjakova et al, 2004) a large number of circuit versions was created by introducing sets of models for every separate fault. In fact, hard faults were considered while the opens and the shorts were modelled by resistors of variable resistivity.…”

“…As shown in the figure (using T 7 as an example) there exist three open-circuit faults (OC) and three short-circuit faults (SC) per transistor (for example, OC3G stands for open gate of transistor T 3 , and SC1DG stands for drain and gate shorted in transistor T 1 , Table 1.). As opposed to (Stopjakova et al, 2004) and some others, the shorts (some of them behaving as bridging fault) and opens were really implemented instead of resistors modelling them. To effectively simulate perfect short and opens we used our model of the ideal switch (Mrčarica et al, 1999) what is not possible in the SPICE simulator.…”

Fault diagnosis of analog circuit based on a second map SVDD

“…Intelligent methods such as neural network (NN), statistical learning theory (SLT) are widely used in fault diagnosis [3][4][5][6][7][8][9]. Various NN methods are employed to improve the diagnosis accuracy and efficiency [4][5][6][7]. However, more fault modes and high-dimension feature data make NN structure complicated, train slowly and converge difficultly.…”

Review of high level fault modeling approaches for mixed-signal systems

“…Structural faults are random defects that cause structural deformations like short and open circuits which change the circuit topology, or cause large variations in design parameters (e.g., a change in the W/L ratio of a transistor caused by a dust particle on a photolithographic mask) [3,4] . In a transistor such as MOS transistor short faults include: Gate-Drain, Gate-Source, Drain-Source Shorts (GDS, GSS, DSS), and Gate-Oxide Short (GOS); Open faults include Drain/Source opens (DOP, SOP) [5] . Parametric faults are caused by statistical fluctuations in the manufacturing environment.…”