Clepsydra: Modeling timing flows in hardware designs

Ardeshiricham, Armaiti; Hu, Wei; Kastner, Ryan

doi:10.1109/iccad.2017.8203772

Cited by 25 publications

(15 citation statements)

References 12 publications

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“…Similar to GLIFT, RTLIFT [279], Clepsydra [280] and VeriSketch [152] are a set of secure hardware design tools that employ fine-granularity security labels and label propagation policies to measure the flow of information but target RTL Verilog designs. RTLIFT has observed ∼5X improvement in verification performance as compared to GLIFT.…”

Section: Hardware Security Tools a Security Verification Toolsmentioning

confidence: 99%

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

Chang

Sengupta

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Section: Hardware Security Tools a Security Verification Toolsmentioning

confidence: 99%

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

Chang

Sengupta

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…This approach has the advantage that existing designs, written in current industry standard hardware description languages, can be validated. The approach has been studied in the literature in a series of papers [17], [18], [19]. Gate level information flow tracking requires tagging source variables with the appropriate level (e.g., "high" or "low") of information, asserting the correct level is maintained for sink variables, and deciding when to conditionally disable the assert or under what circumstances to allow declassification.…”

Section: B Information Flowsmentioning

confidence: 99%

“…Then we generate the antecedent from ω l and check whether it satisfies the requirements (line 16). If yes, we output the new invariant; otherwise, we keep on searching (line [17][18][19].…”

Section: Structural Transformation Passmentioning

confidence: 99%

“…Tracking information flow in hardware. Information Flow Tracking logic can be added at the gate level [17] or register transfer level [49] of a hardware design, and can capture timing flows [18], [19] or data flows [50]. While there is a trade-off to be made between precision and performance [51], [52], these techniques can demonstrate whether sensitive inputs to a design, e.g., the key material input to a cryptographic core, is directly or indirectly visible in the output signals.…”

Section: Language Based Verificationmentioning

confidence: 99%

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Transys: Leveraging Common Security Properties Across Hardware Designs

Zhang

Sturton

2020

2020 IEEE Symposium on Security and Privacy (SP)

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This paper presents Transys, a tool for translating security critical properties written for one hardware design to analogous properties suitable for a second design. Transys works in three passes adjusting the variable names, arithmetic expressions, logical preconditions, and timing constraints of the original property to retain the intended semantics of the property while making it valid for the second design. We evaluate Transys by translating 27 assertions written in a temporal logic and 9 properties written for use with gate level information flow tracking across 38 AES designs, 3 RSA designs, and 5 RISC processor designs. Transys successfully translates 96% of the properties. Among these, the translation of 23 (64%) of the properties achieved a semantic equivalence rate of above 60%. The average translation time per property is about 70 seconds.

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“…Information Flow Tracking (IFT) is a technique to measure flows of digital information through a hardware design by monitoring how data propagates across elements of the design during execution. Recently, IFT has been demonstrated at the RTL (Ardeshiricham et al, 2017b;Hu et al, 2018) and gate level (Hu et al, 2014;Hu et al, 2016;Becker et al, 2017), and has been used to monitor implicit flows through digital side channels (Ardeshiricham et al, 2017a).…”

Section: Introductionmentioning

confidence: 99%

Mining Secure Behavior of Hardware Designs

Deutschbein

2021

Preprint

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Calvin Deutschbein: Mining Secure Behavior of Hardware Designs (Under the direction of Cynthia Sturton)Hardware presents an enticing target for attackers attempting to gain access to a secured computer system. Software-only exploits of hardware vulnerabilities may bypass software level security features. Hardware must be made secure. However, to understand whether a hardware design is secure, security specifications must be generated to define security on that design.Micro-architectural design elements, undocumented or under-documented features, debug interfaces, and information-flow side channels all may introduce new vulnerabilities. The secure behavior of each must be specified in order ensure the design meets its security requirements and contains no vulnerabilities. However, manual efforts can be overwhelmed by design complexity, and many hardware vulnerabilities, such as Memory Sinkhole, SYSRET privilege escalation, and most recently Spectre/Meltdown, persisted in product lines for decades despite extensivetesting. An automated solution is needed to specify secure designs. Specification mining offers a solution by automating security specification for hardware. Specification miners use a form of machine learning to specify behaviors of a system by studying a system in execution. However, specification mining was first developed for use with software. Complex hardware designs offer unique challenges for this technique. Further, specification miners traditionally capture functional specifications without a notion of security, and may not use the specification logics necessary to describe some security requirements.This work demonstrates specification mining for hardware security. On CISC architectures such as x86, I demonstrate that a miner partitioning the design state space along control signals discovers a specification that includes manually defined properties and, if followed, would secure CPU designs against Memory Sinkhole and SYSRET privilege escalation. For temporal propiii

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Clepsydra: Modeling timing flows in hardware designs

Cited by 25 publications

References 12 publications

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

Transys: Leveraging Common Security Properties Across Hardware Designs

Mining Secure Behavior of Hardware Designs

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