CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination

Abstract

Formal equivalence verifiers for combinational circuits rely heavily on BDD algorithms. However, building monolithic BDDs is often not feasible for today's complex circuits. Thus, to increase the effectiveness of BDD-based comparisons, divide-and-conquer strategies based on cut-points are applied. Unfortunately, these algorithms may produce false negatives. Significant effort must then be spent for determining whether the failures are indeed real. In particular, if the design is actually incorrect, many cut-point based algorithms perform very poorly. In this paper we present a new algorithm that completely removes the problem of false negatives by introducing normalized functions instead of free variables at cut points. In addition, this approach handles the propagation of input assumptions to cut-points, is significantly more accurate in finding cut-points, and leads to more efficient counter-example generation for incorrect circuits. Although, naively, our algorithm 1 would appear to be more expensive than traditional cut-point techniques, the empirical data on more than 900 complex signals from a recent microprocessor design, shows rather the opposite.

A signal correlation guided ATPG solver and its applications for solving difficult industrial cases

“…Hence, the random behavior can be a result of the ineffectiveness of the random simulation for uncovering the signal correlations for these examples. One may argue that for those "C-" testcases, although SCGL heuristics are effective, these examples are "easy" problems if an advance equivalence check point matching approach [13] is used. We emphasize that our SCGL heuristics are different from equivalence check point matching.…”

“…Circuit Characteristics: With recent advancements in the field of CEC [12,13] one does not expect to see many difficult signals in a microprocessor for CEC. The number of logic levels that can exist within a pipestage of modern microprocessor designs is limited and therefore sophisticated CEC techniques prove highly efficient.…”

“…Intuitively, this is due to the fact that these circuits contain many re-convergent signals which create false negatives for cut-point techniques that do not offer false negative elimination. On the other hand, employing cut-point based techniques that offer false-negative elimination by employing parametric representations for functions, such as normalized BBDs [13], does not work because of the degree of reconvergence. However, the existence of significant reconvergence is a clear indication that signals in the netlists are highly correlated and this is something that should be exploited to speed up the process of a decision procedure.…”

High capacity and automatic functional extraction tool for industrial VLSI circuit designs

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An Implicit Approach to Minimizing Range-Equivalent Circuits

“…Digital Object Identifier 10.1109/TCAD.2008.2006088 a simplified range-equivalent circuit connected to the cuts to drive the subcircuits [14], [15]. For example, in Fig.…”