Clock and data recovery IC for 40 Gb/s fiber-optic receiver

Georgiou, G.; Baeyens, Y.; Chen, Y.-K.; Groepper, C.; Paschke, P.; Pullela, R.; Reinhold, M.; Dorschky, C.; Mattia, J.P.; Mohrenfels, T.W. von; Schulien, C.

doi:10.1109/gaas.2001.964354

Cited by 10 publications

(4 citation statements)

References 4 publications

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“…Several high speed broadband physical layer circuit blocks for 40 Gbps optic fiber communication links -such as clock-data recovery [8], 4:1 multiplexer and 1:4 demultiplexer [9] -have been demonstrated. In order to drive the high speed electro-optical modulators with advanced optical modulation formats such as optical duobinary and QPSK, the InP DHBT driver amplifiers deliver more than twice the Vpi voltage (~10 volts) to achieve full phase modulation [10].…”

Section: High Performance Digital and Mixed-mode Icsmentioning

confidence: 99%

Recent Advances in III-V Electronics

Chen¹,

Baeyens²,

Weimann³

et al. 2006

IEEE Custom Integrated Circuits Conference 2006

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Compound III-V semiconductor circuits promise fast and power efficient analog, digital and mixed-mode applications. This paper will provide an overview of recent advances in high speed III-V compound devices and integrated circuits for high capacity wireless and optic fiber communications. Several critical compound semiconductor ASIC technologies and their unique performance advantages over prevailing silicon CMOS and SiGe technologies will be illustrated.

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Section: High Performance Digital and Mixed-mode Icsmentioning

confidence: 99%

Recent Advances in III-V Electronics

Chen¹,

Baeyens²,

Weimann³

et al. 2006

IEEE Custom Integrated Circuits Conference 2006

Self Cite

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“…This adjustment will take a finite amount of time, particularly the clock recovery as a correct reconstruction of the data is only possible once the optimum sampling point has been determined, and finally determines the minimum packet or burst length possible in the network. Phase-locked loops (PLLs) have been widely used for clock recovery in transmission systems with bit rates up to 40 Gbit/s, 22 but their frequency acquisition time is typically in the range of several hundred microseconds. 23 Alternatively, for fast acquisition, either fast phase-locking can be used if transmission distances are short, e.g.…”

Section: Burst Mode Receiver and Fast Clock Recoverymentioning

confidence: 99%

<title>Dynamic optical network architectures for future IP traffic</title>

et al. 2004

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Current optical transport networks provide high bandwidth through the use of advanced WDM technology, but are difficult to adapt to the different statistical patterns and quality of service (QoS) demands of future traffic. There has been much debate whether the use of dynamically reconfigurable optical networks would have a number of advantages in accommodating the needs of future traffic demands. Dynamic networks would eliminate the need for frequent opto-electronic conversion in current networks, and may save resources through higher utilization and fast adaptation. Different architectures have been proposed to address this problem: Wavelength-routed optical networks (WRON), optical burst switching (OBS), and optical packet-switching (with increasing granularity and speed of reconfiguration). In this paper we investigate whether these architectures are suitable (necessary?) to meet the demands of future traffic, using an analysis focusing on both modeling and experimental aspects.

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“…Over the pass few decades, high-speed clock and data recovery circuits have been designed mostly using Gallium Arsenide (GaAs), Silicon Germanium (SiGe) and bipolar technologies that are expensive and power-hungry [5][6][7][8][9]. However, the recent emergence of cheap deep sub-micron CMOS technology and the advances in computer-aided design make CMOS technology a possible implementation for a gigahertz, low power circuit that results in the reduction of process and development costs [10].…”

Section: Introductionmentioning

confidence: 99%

Design of high-speed clock and data recovery circuits

Kok-Siang

Sulaiman

Hean-Teik

et al. 2007

Analog Integr Circ Sig Process

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This article describes the various architectures for a high-speed clock and data recovery (CDR) circuit. Following a brief introduction of clock and data recovery circuit, a phase detection circuit, one of the most critical blocks in a CDR that determines not only the performance but also the CDR architecture, is addressed. The descriptions start with the most basic XOR logic up to the phasefrequency detector circuit. Trade-offs of each of the phase detectors are outlined. Two types of dual loop CDR architecture are briefly introduced. Finally, full-rate and half rate CDR architectures are described.

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Clock and data recovery IC for 40 Gb/s fiber-optic receiver

Cited by 10 publications

References 4 publications

Recent Advances in III-V Electronics

Recent Advances in III-V Electronics

<title>Dynamic optical network architectures for future IP traffic</title>

Design of high-speed clock and data recovery circuits

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