Clock distribution on a dual-core, multi-threaded Itanium/spl reg/ family microprocessor

Doyle, B.S.; Mahoney, P.; Fetzer, E.; Naffziger, Samuel

doi:10.1109/icicdt.2005.1502575

Cited by 7 publications

(3 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Comparable solutions offer similar or worse levels of skew reduction, sub-10 ps in a 90-nm technology [64], 70 ps in a 0.18-m technology [2] and 15 ps in a 0.25-m technology [65]. [66] demonstrates a skew reduction scheme capable of reducing skew to within 10% of the clock period, versus under 4% here for the same feature size.…”

Section: Simulation Results For Single Clock Systemmentioning

confidence: 98%

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks

Chattopadhyay

Žilić

2012

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

We present a clock distribution network that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modular, standard cell-based design approach that mitigates the effect of intra-die temperature and process variances. We route the clock line serially, using an averaging technique to eliminate skew between clock regions in a domain. Routing clock lines serially allows optimal wire usage for clock networks by eliminating the redundant wires required to match path delays. Our clock network provides control over regional clock skews, can be used in beneficial skew applications and facilitates silicon-debug. Serial clocking permits the use of routing switches in the clock network and allows post-silicon resizing and reshaping of clock domains. Defective sections of the clock network can be bypassed, providing post silicon repair capability. The system uses a closed-loop synchronization phase to combine the clock skew reduction of an actively synchronized clock network with an open-loop operating phase that minimizes power consumption like passive clock networks. Our clock network provides significant flexibility for application-specific integrated circuit, system-on-chip, and field-programmable gate-array designs, exhibiting good operating characteristics everywhere in the design envelope. Our silicon implementation achieves a maximum edge-to-edge uncertainty of 80 ps for regional clocks, which is roughly equal to the cycle-to-cycle jitter of the on-chip clock source.

show abstract

Section: Simulation Results For Single Clock Systemmentioning

confidence: 98%

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks

Chattopadhyay

Žilić

2012

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…The total clock skew ranges from 3.9 ps to 5.5 ps with an overall power consumption of 62.82 mW, or 4.188 mW per tap. Comparable solutions offer similar or worse levels of skew reduction: sub-10 ps for [16], 70 ps for [5], 28 ps for [17] and 15 ps for [18]; [9] is capable of reducing skew to within 10% of the clock period, versus under 4% here; [1] achieves 3 ps skew resolution by modifying an H-tree and requiring a duplicate co-located return path for all leaves. PLL-based distributions typically consume hundreds of mW [17].…”

Section: Simulation Resultsmentioning

confidence: 99%

Reconfigurable Clock Distribution Circuitry

Chattopadhyay

Žilić

2007

2007 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

Abstract-We present the circuitry required for implementing a multi-clock reconfigurable, reprogrammable clock distribution network for integrated circuits using a reference-based scheme for skew compensation. In the scheme, a device is subdivided into multiple regions and a bi-directional clock distribution line is daisy-chained through the device, connecting each region in the domain. Switching structures that can be used to re-route the clock chain are added where needed. The proposed design simplifies layout for irregularly shaped clock domains and provides flexibility to designers by enabling post-fabrication changes to the clock distribution network. Reconfigurable clock distribution networks can be used in some ASICs, SoCs and FPGAs. The reference-based approach used is applicable to both single and multiple clock distributions.

show abstract

“…In post-silicon, the aim is to derive the best-known recipe based on critical-path delays that are measured on actual silicon. Prior works have used post-silicon tunable clock-tree synthesis to fix timing violation in microprocessor clock design [4], [14]. Nagaraj et al [14] describe a method that uses transition-ATPG patterns to measure delays on an actual tester on any given chip, and then use clock tuning to optimize the frequency of that particular piece of silicon before shipping it to the customer.…”

Section: Introductionmentioning

confidence: 99%

AutoRex: An automated post-silicon clock tuning tool

Tadesse

Grodstein

Bahar

2009

2009 International Test Conference

View full text Add to dashboard Cite

Post-silicon clock-tuning is a technique used as part of speed-debug efforts to increase the allowable clock frequency of a chip. These days, it is not uncommon for high-end microprocessors to have cores containing a few thousand clock-tuning elements (i.e., variable-delay buffers). Each such buffer can be assigned to one of several possible discrete delay values, as part of the post-silicon speed debugging process. With the proper mix of assignments, many chips that initially could not meet targeted speed requirements, can now run within specification. With thousands of tunable buffers available on chip, the possible combination of assignments to the delay values is quite large. In addition, process variation causes the same design, once fabricated into silicon, to have different critical paths across different chips. Thus a specific buffer-delay assignment that most improves clock frequency for some chips may not be optimal for all chips. In this paper, we propose a tool we call AutoRex, that produces clock-tuning assignments automatically. AutoRex operates by taking data from a volume experiment across multiple process corners and analyzes this data using Satisfiability Modulo Theory (SMT) solvers to create a single "recipe" for delay buffer assignments such that the clock frequency of the chip is improved as much as possible over the entire sample of chips. Our results show up to a 9% improvement in frequency using AutoRex.

show abstract

Clock distribution on a dual-core, multi-threaded Itanium/spl reg/ family microprocessor

Cited by 7 publications

References 1 publication

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks

Reconfigurable Clock Distribution Circuitry

AutoRex: An automated post-silicon clock tuning tool

Contact Info

Product

Resources

About