Clock recovery circuits with instantaneous locking

Banu, M.; Dunlop, A.E.

doi:10.1049/el:19921366

Cited by 38 publications

(17 citation statements)

References 1 publication

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“…Although signals may be retimed using distributed phase-locked loops [19] and all-optical delays [20], such techniques restrict the total circumference of the metro ring due to a combination of phase noise, maximum delay tunability, and fly-back. For a burst-switched network, however, an incoming data burst may be simultaneously sampled at multiple clock phases [21], and subsequently, the optimum clock phase is selected for onward processing. Such a scheme may be developed for use in optical systems [11][12][13] and may also provide partial regeneration of the incoming signal.…”

Section: Wdm-to-otdm Conversionmentioning

confidence: 99%

Optical interconnection of core and metro networks [Invited]

et al. 2008

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͑Doc. ID 99278͒A network concept is introduced that exploits transparent optical grooming of traffic between an access network and a metro core ring network. This network is enabled by an optical router that allows bufferless aggregation of metro network traffic into higher-capacity data streams for core network transmission. A key functionality of the router is WDM to time-division multiplexing (TDM) transmultiplexing.

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Section: Wdm-to-otdm Conversionmentioning

confidence: 99%

Optical interconnection of core and metro networks [Invited]

et al. 2008

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“…A minimum of four sampling clock phases is required for good error rate performance in the case of ideal gates [4]. Appropriate realizations have been established electronically [5] and optically [6]. The optical realisation [named Asynchronous Digital Optical Regenerator (ADORE)] uses two bi-directional electro-absorption modulator (EAM)-loops.…”

Section: Introductionmentioning

confidence: 99%

Asynchronous Digital Optical Regenerator for 4 × 40 Gbit/s WDM to 160 Gbit/s OTDM Conversion

Chow¹,

Ellis²,

Cotter³

2007

Opt. Express

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Abstract:We propose and numerically analyse an asynchronous digital optical regenerator using a single-EAM loop and a novel neighbor-combine approach. It effectively re-synchronizes input signals with arbitrary phases to the local clock, and regenerates signals with high amplitude fluctuation and polarization mode dispersion. We demonstrate the application of this regenerator for 4×40 Gbit/s WDM to 160 Gbit/s OTDM conversion.

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“…timing configuration for the DSM clocks. The DSM output bitstream modulates a simple on-off keyed (OOK) transmitter or is saved to non-volatile memory (not shown).The CDR circuit is composed of a charge pump phase-locked loop (PLL), two interleaved replica VCOs and digital logic [4,5]. The VCOs are built from 161-stage ring oscillators with internal RC loading provided by NMOS switches and capacitors.…”

mentioning

confidence: 99%

“…The CDR circuit is composed of a charge pump phase-locked loop (PLL), two interleaved replica VCOs and digital logic [4,5]. The VCOs are built from 161-stage ring oscillators with internal RC loading provided by NMOS switches and capacitors.…”

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confidence: 99%

Ultra-low-voltage circuits for sensor applications powered by free-space optics

Kleeburg

Loo

Guilar

et al. 2010

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

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Advances in photonics have typically been exploited in high performance systems, e.g. high-frequency, low-jitter clocks injected optically [1]. As solid-state lighting and free-space optical (FSO) communication expand, low-performance sensor systems can also benefit from photonics. Sensors can receive power, clock, and data from optical sources at different wavelengths with crosstalk eliminated through narrowband filtering by photonic devices (e.g., ring resonators [2]). Applications include indoor environmental sensing or biomedical devices implanted under the skin (transcutaneous optical power). However, significant challenges to realizing such systems exist. FSO power decreases quadratically (beam divergence) and exponentially (absorption) with distance, thus optically-powered sensors must be extremely low power to maximize operating range. Mixed-signal circuits must support energy-scalable operation with low area overhead (to maximize energy harvesting photodiode area) under variable low voltage (V DD can vary significantly with light intensity near the maximum power point). They must process analog inputs near full-scale to maximize SNR. Energy harvesting photodiodes optimized for conventional CMOS have been developed [3]. In this paper, we describe optically-powered CDR and delta sigma modulator (DSM) circuits. Figure 27.9.1 shows a possible system context. Photodiodes supply power (from ambient light or interrogating beam) and capture optical data, e.g. timing configuration for the DSM clocks. The DSM output bitstream modulates a simple on-off keyed (OOK) transmitter or is saved to non-volatile memory (not shown).The CDR circuit is composed of a charge pump phase-locked loop (PLL), two interleaved replica VCOs and digital logic [4,5]. The VCOs are built from 161-stage ring oscillators with internal RC loading provided by NMOS switches and capacitors. RC loading ensures balanced rise and fall times and a minimum oscillating frequency across a wide range of supply voltages. Figure 27.9.2 shows a block diagram of the circuit, a schematic of VCO R and an example of a delay stage inside the oscillator. The data rate is carefully chosen near the minimum frequency attainable by VCO R , and the data is 3b4b encoded to maximize transitions. VCO R output signal R is compared to the REF signal by the Phase Frequency Detector (PFD). After a sufficient number of transitions, the PLL will have adjusted the frequency produced by VCO R such that it approximately equals the data rate. The frequency output by VCO T and VCO C should also match the data rate since all VCOs are identical and have the same control voltage, V tune . The data D IN interleaves VCO T and VCO C producing the pulses T and C. These are XOR'ed to produce the recovered clock CLK, which samples D IN on the falling edge. The retimed data D OUT now has the rising edge of the recovered clock aligned in the center of the data. Mismatch in the VCO frequencies at fixed V tune will produce a frequency deviation from the data rate. This poses a large problem in...

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Clock recovery circuits with instantaneous locking

Cited by 38 publications

References 1 publication

Optical interconnection of core and metro networks [Invited]

Optical interconnection of core and metro networks [Invited]

Asynchronous Digital Optical Regenerator for 4 × 40 Gbit/s WDM to 160 Gbit/s OTDM Conversion

Ultra-low-voltage circuits for sensor applications powered by free-space optics

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