Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing

Zhang, Yucong; Wen, Xin; Holst, Stefan; Miyase, Kohei; Kajihara, Seiji; Wunderlich, Hans-Joachim; Qian, Jun

doi:10.1109/ats.2018.00037

Cited by 6 publications

(6 citation statements)

References 23 publications

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“…reg s_axis_tvalid = 1'b0; reg [15:0] prescale = 0; wire s_axis_tready; wire txd; wire busy; To avoid errors resulting from the fusion of two data sets, the data in data signal will be kept in r_data. A low state level denotes an idle state, a high level denotes a working state, and state signifies the working state [13]. The send flag is represented by bit_flag, the bit counter by bit_cnt, and the baud rate counter by baud_cnt.…”

Section: Experiments Codes 61 Uart Transmitter Modulementioning

confidence: 99%

“…whereas in this project UART with RS232 standard is uses for transmission of data signal which gives some advantages over a conventional UART. UART with RS232 operates on the principle of asynchronous meaning that the data is transmitted individual bits without the need for continuous clock signal.RS232 is able to communicate up to 15 m at a rate of 1.492 kpbs without any interruption between two devices [15].…”

Section: Introductionmentioning

confidence: 99%

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Design and Implementation of Verilog Based High Speed Low Power UART

Ms. Banti Kumari,

Ms. Kanika Jindal,

Mr. Amit Bindal

2024

Int Res J Adv Engg Hub

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The most crucial component of serial communication is a microcircuit called a universal asynchronous receiver/transmitter (UART). Receive-transmitter asynchronous technology is known as UART, and it is widely used for device-to-device communication protocols. Using asynchronous serial communication at a speed that can be adjusted. A hardware communication technique called UART Asynchronous conditions occur when the output of the transmitting device and the receiving end are not in sync with a clock. In UART, receiving a signal is known as RxD, and transmitting a signal is known as TxD. In comparison to the existing conventional UART design, we were able to reduce delay by 29% and power usage by 33% using our approach. The effectiveness of the novel UART design is noticed with the reduction in delay and power consumption. Synthesis and simulation are done in Xilinx ISE and Modelsim and Verilog HDL is used to implement a unique UART design.

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Section: Experiments Codes 61 Uart Transmitter Modulementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Verilog Based High Speed Low Power UART

Ms. Banti Kumari,

Ms. Kanika Jindal,

Mr. Amit Bindal

2024

Int Res J Adv Engg Hub

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“…Scan stitching proposed in [33] Figure 5. Data corruption due to simultaneous shifting of chains [34] Zhang et al [35] extended the technique to mitigate shift timing failures caused by excessive IR-drop on clock buffers. Similar to [34], it uses netlist and layout information.…”

Section: Ordering Chains Based On Logic Connectivitymentioning

confidence: 99%

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

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While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

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“…In functional and test modes, a speed improvement was seen. The necessity of partial shift is described in [6], as well as how it reduces global switching activity and, thus, power consumption. It is shown that high heat dissipation increases clock skew, IR drop on clock buffers in the clock tree, and the chance of shift failures.…”

Section: Literature Surveymentioning

confidence: 99%

“…Since test patterns are not stored in memory, memory attacks are also impossible. Scan chains can be employed in [8] to access data in embedded systems' crypto-processors. As a result, this paper suggests that during test mode, control data and output data be encrypted.…”

Section: Literature Surveymentioning

confidence: 99%

Low Power Full Scan Architecture for UART Module

Abhinav¹,

Kiran²

2022

Int J Res Rev

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Modern SoCs feature a complicated design made up of many macros that are in charge of various tasks carried out by an application. The effort required for the verification and testing of a specific product grows as a result of the requirement for more raw computing power and an increase in integration density. The testability of the communication modules is required because SoCs contain several communication modules that, if they fail, could render the SoC worthless. The full scan architecture for a full-duplex UART module is the one that is being suggested. The work displays the power savings for both manually and automatically inserted scan chains that were based on the system partition algorithms. While manually placed scan chains achieved peak power reduction of 74.9 percent in comparison to automatic scan chains, the automatically inserted scan chains have less area with higher activity. Keywords: Low power, full scan, UART, DFT, System partition algorithms

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Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing

Cited by 6 publications

References 23 publications

Design and Implementation of Verilog Based High Speed Low Power UART

Design and Implementation of Verilog Based High Speed Low Power UART

Developments in scan shift power reduction: a survey

Low Power Full Scan Architecture for UART Module

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