Clock Synchronization Errors in Circuits: Models, Stability and Fault Detection

Abstract

This paper models and analyzes the effect of multiple sub-systems that are driven by the same clock signal with active clock edges reaching subsystems at different time instants. This type of problem appears in high speed circuits and systems where the clock signal propagation delays differ significantly and the global system properties of the ideally synchronously switching system are changed. Fault detection and identification methods for this type of system are provided, by using a state-space approach to asynchronously switching systems.

New Challenges in Dynamical Systems: The Networked Case

“…For details on modeling, stability and performance of these systems see, (Lorand and Bauer, 2005;Lorand and Bauer, 2006a;Lorand and Bauer, 2006b). …”

Determination of Clock Synchronization Errors in Distributed Networks

“…Clock synchronization has been discussed intensively in the area of theoretical computer science especially in the 1980's [11,23], and various impossibility results and bounds for synchronization errors have been reported [15,14]. More recently, with the growing interest in the application of large-scale networks, in particular ad hoc and sensor networks, clock synchronization problems have attracted considerable attention [16,1,20,17,13,25].…”

Stability and robustness of systems with synchronization errors

“…It was shown in [5] that most synchronous systems totally change their response if operated asynchronously. Even stability is often lost [5]- [6] and there is generally no stability robustness with respect M. Przedwojski to synchronization errors, with the exception of work in [7], [8] that are very limited in terms of application to practically relevant cases.…”

“…Asynchronous switching in a linear timeinvariant systems is discussed in, for example, [6], [7] and here we begin from the problem setup considered in this previous work. We consider the case where every state vector entry x i is fed by a clock with rate T i , i = 1, 2, ..., n. The clock rates are equal (T i = T, i = 1, 2, ..., n) but the associated signals are out of phase.…”

“…In order to capture effects of asynchronous switching, an event driven time index k is introduced, which is increased by an integer equal to the number of variables that switch simultaneously. Following [6] we assume that after each switching event the time index is incremented by the number of simultaneously switching variables. Consequently over a full clock period the time index is incremented by n, but there is no information about the order in which these variables have been updated.…”