Clock tree synthesis with methodology of re-use in 3D IC

Chen, Fu-Wei; Hwang, TingTing

doi:10.1145/2228360.2228559

Cited by 7 publications

(2 citation statements)

References 8 publications

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“…The authors in [16] proposed a design methodology of a global clock tree construction in 3D IC. The objective of their design was to extend an existing clock tree in 2D IC to 3D IC with consideration of wire length, clock skew and the number of TSVs.…”

Section: Literature Surveymentioning

confidence: 99%

An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC

Mondal

Chatterjee²,

Samanta

2018

IET Computers & Digital Techniques

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Effective clock tree design is an important factor for determining chip performance. In this study, the authors present a 3D clock tree design algorithm to enhance the speed and performance of a VLSI chip. The authors propose an algorithm to determine the performance of the clock network by optimising both the clock skew and the dynamic power consumption of the 3D IC clock tree. The authors propose an algorithm for clock tree design based on the Elmore Delay method and routes all the sinks efficiently considering the obstacles with the use of an optimum number of through-silicon-vias (TSVs). The proposed method starts with a segregation technique to divide the sinks into smaller zones. Subsequently, an obstacle avoiding abstract clock tree is constructed with a minimum number of TSVs and buffers. The skew and dynamic power of the tree is calculated. Consequently, the proposed method is compared with recent existing works. The experimental results so obtained are quite encouraging. Nomenclature SinkNode set of sinks die no number of die or stack s n any sink ∈ SinkNode x i , y i coordinates of sink s i Sink NEB , Sink NWB , Sink SEB , Sink SWB set of sinks at direction North East, North West, South East and South West Block, respectively (x lc , y lc) location of centre with x,y position WL wire length Res resistance Cap capacitance

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Section: Literature Surveymentioning

confidence: 99%

An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC

Mondal

Chatterjee²,

Samanta

2018

IET Computers & Digital Techniques

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“…Clock buffers are inserted along the wire to control latency and slew rate, while TSV-buffers are inserted just at each internal node for pre-bond testability. Different from the existing 3D design, which focused on slew-aware buffer insertion during the bottom-up embedding procedure of DME [5,11,12], our slew-aware buffering is performed after clock routing for the following reasons: 1) it is easy to achieve with an O(n) time complexity; 2) the buffer delay may change under different supply voltage, so exact zero skew numerical buffer solution during bottom-up embedding procedure of DME under one supply voltage may change under another. In our slew-aware buffering algorithm, clock buffers are added along the clock paths so that the downstream capacitance of each buffer is limited to the bounding condition, which is denoted as CMAX in literature [5].…”

Section: E Slew-aware Bufferingmentioning

confidence: 99%

Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis

Liu

Wang

et al. 2015

IEEE Trans. VLSI Syst.

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Through-silicon via (TSV) could provide vertical connections between different dies in three-dimensional integrated circuits (3D ICs), but the significant silicon area occupied by TSVs may bring great challenge to designers in 3D clock tree synthesis (CTS) because only few whitespace blocks can be used for clock TSVs after floorplan and placement. Unlike most of the published previous works that ignore whitespace, this paper for the first time proposes a whitespace-aware TSV arrangement algorithm in 3D CTS. The algorithm consists of three stages: sink pre-clustering, whitespace-aware threedimensional method of means and medians (3D-MMM) topology generation and deferred-merge embedding (DME) merging segment reconstruction. We also present a TSV whitespaceaware 3D CTS flow. Experiment results show that our proposed algorithm is more practical and efficient, the average skew and power can be reduced by 49.2% and 1.9% respectively, compared to the traditional 3D-MMM based CTS method with TSV moving adjustment.

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