Clocking arbitrarily large computing structures under constant skew bound

El-Amawy, A.

doi:10.1109/71.210808

Cited by 9 publications

(13 citation statements)

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“…The nodes also are responsible for clocking the data processors or cells (processors hereafter). Although a clock node could clock more than one processor, [3], [4] we assume here that each node is assigned to a unique processor and each processor is assigned a unique node. In this paper we only consider clocking a 2-D mesh of processors.…”

Section: Tree Clocking Networkmentioning

confidence: 99%

“…[6], [3]. The above also guarantees that the skew between outputs of any two nodes in the same cycle is < (L 1)A.…”

Section: Tree Clocking Networkmentioning

confidence: 99%

“…The problem clock skew poses is that it directly relates to the clocking rate. Larger skew requires slower clock rate for the system to operate correctly [8], [1], [3]. It has been shown that, for a synchronous system to operate properly, the minimum clock period must be extended by the amount of the largest anticipated clock skew in the system [8], [3].…”

mentioning

confidence: 99%

“…Larger skew requires slower clock rate for the system to operate correctly [8], [1], [3]. It has been shown that, for a synchronous system to operate properly, the minimum clock period must be extended by the amount of the largest anticipated clock skew in the system [8], [3]. In other words, if system A which is skew-free can safely operate with a minimum clock period of T, then a similar system B which suffers from skew <must use a clock period > T + -.…”

mentioning

confidence: 99%

“…In a recent development, E1-Amawy [3]- [5] proposed a new clock distribution scheme called Branch-and-Combine clocking. The most interesting feature of the scheme is that clock skew is guaranteed to have a constant upper bound regardless of network size.…”

mentioning

confidence: 99%

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A Comparative Study of SynchronousClocking Schemes for VLSI Based Systems

El-Amawy

Maheshwar

1993

VLSI Design

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Recently a novel clock distribution scheme called Branch-and-Combine(BaC) has been proposed. The scheme guarantees constant skew bound irrespective of the size of the clocked network. It utilizes simple nodes to process clock signals such that clock paths are adaptively selected to guarantee constant skew bound. The paper uses a VLSI model to compare the properties of the new scheme to those of the well established H-Tree approach. The H-Tree is a binary tree of simple buffers which is laid out such that leaves are at equal distances from the root. Our study considers clocking 2-D processor meshes of arbitrary sizes. We evaluate and compare the relevant parameters of both schemes in a VLSI layout context. We utilize parameters such as clock skew, link costs, node costs and area efficiency as the basis for comparison. We show that for each BaC network, there is a certain threshold size after which it outperforms the corresponding tree network in terms of skew. We also show that except for node costs, BaC networks outperform the H-Tree, especially when the size of the clocked network is large. As an extension we show that BaC clocking does not suffer from potential pulse disappearance, no matter how large the network is.

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Section: Tree Clocking Networkmentioning

confidence: 99%

“…[6], [3]. The above also guarantees that the skew between outputs of any two nodes in the same cycle is < (L 1)A.…”

Section: Tree Clocking Networkmentioning

confidence: 99%